Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC18F23K20T-I/MV 数据手册 > PIC18F23K20T-I/MV 其他数据使用手册 3/9 页
器件3D模型￥ 4.237
PIC18F23K20T-I/MV 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
UQFN-28
描述:
PIC 64MHz 闪存：4K@x16bit RAM：512Byte
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
封装信息在P6
导航目录
PIC18F23K20T-I/MV数据手册
Page:
of 9 Go
若手册格式错乱，请下载阅览PDF原文件
2009-2015 Microchip Technology Inc. DS80000469E-page 3
PIC18F23/43K20
Silicon Errata Issues
1. Module: BOR
An unexpected Brown-out Reset may occur when
enabling the comparator with the Fixed Voltage
Reference (FVR) selected as the VIN+ input.
Work around
Disconnect the FVR from the VIN+ comparator
inputs prior to enabling the comparator and then
reconnect it after enabling the comparator.
Affected Silicon Revisions
2. Module: Comparator
There may be a glitch on the comparator output
when both the comparator and the ADC are
using the Fixed Voltage Reference (FVR) as an
input and the ADC is enabled, disabled, or starts
a conversion.
Work around
Do not use the FVR as an input to both the
comparator and the ADC at the same time.
Affected Silicon Revisions
3. Module: ECCP
Changing direction in Full-Bridge mode inserts a
dead band time of 4/F
OSC *(TMR2Prescale)
instead of 1/F
OSC * (TMR2 Prescale) as specified
in the data sheet.
Work around
None.
Affected Silicon Revisions
PIC18F23/43K20
4. Module: ECCP
In Full-Bridge mode when PR2 = CCPR1L and
DC1B<1:0> = 00 and the direction is changed
then the dead time before the modulated output
starts is compromised. The modulated signal
improperly starts immediately with the direction
change and stays on for
Tosc * TMR2Presale * DC1B<1:0>.
Work around
Avoid changing direction when the duty cycle is
within three Least Significant steps of 100% duty
cycle. Instead, clear the DC1B<1:0> bits before
the direction change and then set them to the
desired value after the direction change is
complete.
Affected Silicon Revisions
PIC18F23/43K20
5. Module: MSSP (SPI clock)
When the SPI clock is configured for Timer2/2
(SSPCON1<3:0> = 0011), and the CKE bit of the
SSPSTAT register is ‘1’, then when SSPBUF is
written the SCK output is improperly and immedi-
ately driven to the non-Idle state together with the
MSb value of the SSPBUF. The duration at which
SDO and SCK remain at these levels may be
shorter than a full half-bit period. The remaining
bits in the byte are output properly.
Work around
None.
Affected Silicon Revisions
PIC18F23/43K20
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (B0).
A0 A1
B0
XX
A0 A1 B0
X
A0 A1 B0
XX
X
A0 A1 B0
XX
X
A0 A1
B0
XX
X
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
