Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC18F24K20-I/SP 数据手册 > PIC18F24K20-I/SP 其他数据使用手册 5/18 页
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PIC18F24K20-I/SP 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
DIP-28
描述:
MICROCHIP PIC18F24K20-I/SP 微控制器, 8位, 闪存, AEC-Q100, PIC18FxxKxx, 64 MHz, 16 KB, 768 Byte, 28 引脚, DIP
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电气规格在P14
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PIC18F24K20-I/SP数据手册
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若手册格式错乱，请下载阅览PDF原文件
2008-2013 Microchip Technology Inc. DS80000425K-page 5
PIC18F24K20/25K20/44K20/45K20
7. Module: MSSP I
2
C
I
2
C Master mode is not functional (Rev. A4 only).
Work around
Use software to emulate Master mode.
Affected Silicon Revisions
8. Module: MSSP SPI
In SPI Master mode, when the CKE bit is cleared
and the SMP bit is set, the last bit of the incoming
data stream (bit 0) at the SDI pin will not be
sampled properly.
Work around
None.
Affected Silicon Revisions
9. Module: MSSP SPI
In SPI Master mode, when CKE bit is set, the
SSPBUF will reload the SSPSR output shift
register on every high-to-low transition of the SS
pin.
Work around
Avoid using the SS pin when the CKE bit is set and
the MSSP is configured for SPI Master mode.
Affected Silicon Revisions
10. Module: MSSP SPI
When SPI is enabled in Master mode with
CKE = 1 and CKP = 0, a 1/F
OSC wide pulse will
occur on the SCK pin.
Work around
Configure SCK pin as an input until after the MSSP
is setup.
Affected Silicon Revisions
11. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to an odd number, the duty cycle of the CK
output will be skewed by one baud clock count.
Work around
High values of SPBRG will minimize the effect of
this anomaly.
Affected Silicon Revisions
12. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to 3 and the TXREG is written while the
previous character is still in the TX shift register,
the LS bit of the TXREG character may be
corrupted during transmission.
Work around
When SPBRG is set to 3, wait until the TRMT bit of
the TXSTA register is set before loading TXREG
with the next character to be transmitted.
Affected Silicon Revisions
13. Module: EUSART
In Synchronous Master mode, if the SPBRG
register is equal to 0 when the TXEN bit is set, then
writing to TXREG will properly start transmission.
However, the clock will be improperly out of phase
with the data bits and the clock will not stop at the
end of the character transmission.
Work around
Set SPBRG register to non-zero value before
setting the TXEN bit.
Affected Silicon Revisions
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
X
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
0xA
0xC
0xE
0x11
0x16
0x18
0x19
0x1B
0x1C
XXXX
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