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PIC18F4480-E/PT 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
TQFP-44
描述:
PIC18F2480/2580/4480/4580 8 位闪存微控制器### PIC18 微控制器
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PIC18F4480-E/PT数据手册
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© 2007 Microchip Technology Inc. DS80219E-page 1
PIC18F2480/2580/4480/4580
The PIC18F2480/2580/4480/4580 Rev. A1 parts you
have received conform functionally to the Device Data
Sheet (DS39637C), except for the anomalies
described below. Any Data Sheet Clarification issues
related to the PIC18F2480/2580/4480/4580 will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.
All of the issues listed here will be addressed in future
revisions of the PIC18F2480/2580/4480/4580 silicon.
The following silicon errata apply only to
PIC18F2480/2580/4480/4580 devices with these
Device/Revision IDs:
1. Module: ECCP
When operating either Timer1 or Timer3 as a
counter with a prescale value other than 1:1 and
operating the ECCP in Compare mode with the
Special Event Trigger (CCP1CON bits,
CCP1M3:CCP1M0 = 1011), the Special Event
Trigger Reset of the timer occurs as soon as there
is a match between TMRxH:TMRxL and
CCPR1H:CCPR1L.
This differs from the PIC18F458, where the Special
Event Trigger Reset of the timer occurs on the next
rollover of the prescale counter, after the match
between TMRxH:TMRxL and CCPR1H:CCPR1L.
Work around
To achieve the same timer Reset period on the
PIC18F4580 family as the PIC18F458 family for a
given clock source, add 1 to the value in
CCPR1H:CCPR1L. In other words, if
CCPR1H:CCPR1L = x for the PIC18F458, to
achieve the same Reset period on the PIC18F4580
family, CCPR1H:CCPR1L = x + 1, where the
prescale is 1, 2, 4 or 8 (depending on the
T1CKPS1:T1CKPS0 bit values).
Date Codes that pertain to this issue:
All engineering and production devices.
2. Module: EUSART
When performing back-to-back transmission in
9-bit mode (TX9D bit in the TXSTA register is
set), an ongoing transmission’s timing can be
corrupted if the TX9D bit (for the next transmis-
sion) is not written immediately following the
setting of TXIF. This is because any write to the
TXSTA register results in a reset of the Baud
Rate Generator which will effect any ongoing
transmission.
Work around
Load TX9D just after TXIF is set, either by polling
TXIF or by writing TX9D at the beginning of the
Interrupt Service Routine, or only write to TX9D
when a transmission is not in progress
(TRMT = 1).
Date Codes that pertain to this issue:
All engineering and production devices.
3. Module: Timer1/Timer3
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen the
duration of the period between the increments of
the timer for the period in which TMR1H/TMR3H
was written. It does not change the actual prescale
value.
Work around
Do not write to TMR1H/TMR3H while Timer1/
Timer3 is running, or else write to TMR1L/TMR3L
immediately following a write to TMR1H/TMR3H.
Do not write to TMR1H/TMR3H and then wait for
another event before also updating TMR1L/
TMR3L.
Date Codes that pertain to this issue:
All engineering and production devices.
Part Number Device ID Revision ID
PIC18F2480 01 1010 100 00001
PIC18F2580 01 1010 110 00001
PIC18F4480 01 1010 101 00001
PIC18F4580 01 1010 100 00001
The Device IDs (DEVID1 and DEVID2) are located at
addresses 3FFFFEh:3FFFFFh in the device’s
configuration space. They are shown in hexadecimal
in the format “DEVID2 DEVID1”.
PIC18F2480/2580/4480/4580 Rev. A1 Silicon Errata
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