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PIC18F4585-E/ML 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
QFN-44
描述:
PIC18F4585-E/ML 管装
Pictures:
3D模型
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PIC18F4585-E/ML数据手册
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若手册格式错乱，请下载阅览PDF原文件
PIC18F2585/2680/4585/4680
DS80283E-page 2 © 2007 Microchip Technology Inc.
5. Module: ECCP
The auto-shutdown source, FLT0, has inverse
polarity from the description in Section 16.4.7
“Enhanced PWM Auto-Shutdown” of the Device
Data Sheet. A logic high-voltage level on FLT0 will
generate a shutdown on ECCP1.
Work around
Invert the logic in the program’s source code.
Date Codes that pertain to this issue:
All engineering and production devices.
6. Module: ECCP
If a Halt command is issued while debugging with
the In-Circuit Debugger (MPLAB
®
ICD 2), the
ECCP module may freeze completely. However, if
a shutdown is enabled and triggered by the FLT0
pin, the ECCPASE bit is set and the outputs are
driven to their shutdown state, as defined by the
PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits,
regardless of the debugging process being
stopped.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
7. Module: ECCP
In 10-Bit Addressing mode, when a Repeated Start
is issued followed by the high address byte and a
Write command, an ACK is not issued.
Work around
There are two work arounds available:
1. Single-Master Environment:
In a single-master environment, the user must
issue a Stop, then a Start, followed by a write
to the address high, then the address low
followed by the data.
2. Multi-Master Environment:
In a multi-master environment, the user must
issue a Repeated Start, send a dummy Write
command to a different address, issue another
Repeated Start and then send a write to the
original address. This procedure will prevent
loss of the bus.
Date Codes that pertain to this issue:
All engineering and production devices.
8. Module: ECCP
When operating either Timer1 or Timer3 as a
counter with a prescale value other than 1:1 and
operating the ECCP in Compare mode with the
Special Event Trigger (CCP1CON bits
CCP1M3:CCP1M0 = 1011), the Special Event
Trigger Reset of the timer occurs as soon as there
is a match between TMRxH:TMRxL and
CCPR1H:CCPR1L.
This differs from the PIC18F458, where the Special
Event Trigger Reset of the timer occurs on the next
rollover of the prescale counter, after the match
between TMRxH:TMRxL and CCPR1H:CCPR1L.
Work around
To achieve the same timer Reset period on the
PIC18F4680 family as the PIC18F458 family for a
given clock source, add 1 to the value in
CCPR1H:CCPR1L. In other words, if
CCPR1H:CCPR1L = x for the PIC18F458, to
achieve the same Reset period on the PIC18F4680
family, CCPR1H:CCPR1L = x + 1, where the
prescale is 1, 2, 4 or 8 (depending on the
T1CKPS1:T1CKPS0 bit values).
Date Codes that pertain to this issue:
All engineering and production devices.
9. Module: ECCP and CCP
When ECCP1 and CCP2 are configured for PWM
mode with 1:1 Timer2 prescaler and duty cycle set
to the period minus 1, this may result in the PWM
output(s) remaining at a logic low level.
Clearing the PR2 register to select the fastest
period may also result in the output(s) remaining at
a logic low output level.
Work around
To ensure a reliable waveform, verify that the
selected duty cycle does not equal the 10-bit
period minus 1 prior to writing these locations, or
use 1:4 or 1:16 Timer2 prescale. Also, verify the
PR2 register is not written to 00h.
All other duty cycle and period settings will function
as described in the Device Data Sheet.
The ECCP and CCP modules remain capable of
10-bit accuracy.
Date Codes that pertain to this issue:
All engineering and production devices.
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