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PIC18F46K20-I/P 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
PDIP-40
描述:
MICROCHIP PIC18F46K20-I/P 微控制器, 8位, 闪存, AEC-Q100, PIC18FxxKxx, 64 MHz, 64 KB, 3.84 KB, 40 引脚, DIP
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PIC18F46K20-I/P数据手册
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若手册格式错乱，请下载阅览PDF原文件
PIC18F26K20/46K20
DS80000379C-page 4 2008-2015 Microchip Technology Inc.
Silicon Errata Issues
1. Module: ECCP
Changing the CCP1M<3:0> bits of CCP1CON
may cause the CCPR1H and CCPR1L registers to
capture the value of Timer1.
Work around
Halt Timer1 before changing ECCP mode. Reload
Timer1 with desired value after ECCP is setup and
before Timer1 is restarted.
Affected Silicon Revisions
2. Module: ECCP
Changing direction in Full-Bridge mode does not
insert dead time between changing the active
drivers in common legs of the bridge.
Work around
None.
Affected Silicon Revisions
3. Module: MSSP I
2
C
Slew rate is slower than I
2
C specifications when
the SLRCON<2> bit is set.
Work around
Clear SLRCON<2> bit when using the I
2
C
peripheral.
Affected Silicon Revisions
4. Module: ADC
Offset error is 3 LSb typical, 7 LSb maximum,
including an acquisition time dependent
component (~2 LSb).
Work around
The time dependent error is insignificant when the
time between conversions is less than 100 ms.
When the time since the previous conversion is
greater than 100 ms then take two ADC
conversions and discard the first.
Affected Silicon Revisions
5. Module: MSSP I
2
C
If a new address byte is received while the BF flag
is set, the SSPOV bit is set and an ACK is not
generated, both of which are proper operation. If
only the SSPOV bit is set (BF flag was cleared)
and a matching address is clocked in, that
received byte will be loaded into the SSPBUF
register and an ACK will be generated, both of
which are improper operation.
Work around
None.
Affected Silicon Revisions
6. Module: MSSP I
2
C
In Master I
2
C mode, when a slave device releases
the clock after holding it low (clock stretching), the
pulse width of the first high clock cycle may be
shorter than half the clock period.
Work around
None.
Affected Silicon Revisions
7. Module: MSSP I
2
C
In Master I
2
C mode, baud rates obtained by
setting SSPADD to a value less than 0x03 will
cause unexpected operation.
Work around
Ensure SSPADD is set to a value greater than or
equal to 0x04.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A5).
A4
A5
X
X
A4
A5
X
X
A4
A5
X
X
A4 A5
X
X
A4
A5
X
X
A4
A5
X
X
A4 A5
X
X
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