Datasheet 搜索 > 微控制器 > Microchip（微芯） > PIC18F46K20-I/PT 数据手册 > PIC18F46K20-I/PT 其他数据使用手册 5/12 页
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PIC18F46K20-I/PT 其他数据使用手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
TQFP-44
描述:
MICROCHIP PIC18F46K20-I/PT 微控制器, 8位, 闪存, AEC-Q100, PIC18FxxKxx, 64 MHz, 64 KB, 3.84 KB, 44 引脚, TQFP
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封装信息在P9
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PIC18F46K20-I/PT数据手册
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of 12 Go
若手册格式错乱，请下载阅览PDF原文件
2008-2015 Microchip Technology Inc. DS80000379C-page 5
PIC18F26K20/46K20
8. Module: MSSP SPI
When the SPI clock is configured for Timer2 output/2
(SSPCON1<3:0> = 0011), the first SPI high time
may be short.
Work around
Option 1: Ensure TMR2 value rolls over to zero
immediately before writing to SSPBUF.
Option 2
: Turn Timer2 off and clear TMR2 before
writing SSPBUF. Enable TMR2 after SSPBUF is
written.
Affected Silicon Revisions
9. Module: MSSP SPI
In SPI Master mode, when the CKE bit is cleared
and the SMP bit is set, the last bit of the incoming
data stream (bit 0) at the SDI pin will not be
sampled properly.
Work around
None.
Affected Silicon Revisions
10. Module: MSSP SPI
In SPI Master mode, when CKE bit is set, the
SSPBUF will reload the SSPSR output shift register
on every high-to-low transition of the SS
pin.
Work around
Avoid using the SS pin when the CKE bit is set and
the MSSP is configured for SPI Master mode.
Affected Silicon Revisions
11. Module: MSSP SPI
When SPI is enabled in Master mode with
CKE = 1 and CKP = 0, a 1/F
OSC wide pulse will
occur on the SCK pin.
Work around
Configure the SCK pin as an input until after the
MSSP is setup.
Affected Silicon Revisions
12. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to an odd number, the duty cycle of the CK
output will be skewed by one baud clock count.
Work around
High values of SPBRG will minimize the effect of
this anomaly.
Affected Silicon Revisions
13. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to 3 and the TXREG is written while the
previous character is still in the TX shift register, the
LS bit of the TXREG character may be corrupted
during transmission.
Work around
When SPBRG is set to 3, wait until the TRMT bit of
the TXSTA register is set before loading TXREG
with the next character to be transmitted.
Affected Silicon Revisions
14. Module: EUSART
In Synchronous Master mode, if the SPBRG
register is equal to 0, when the TXEN bit is set,
then writing to TXREG will properly start
transmission. However, the clock will be
improperly out of phase with the data bits and the
clock will not stop at the end of the character
transmission.
Work around
Set SPBRG register to non-zero value before
setting the TXEN bit.
Affected Silicon Revisions
A4 A5
X
X
A4
A5
X
X
A4
A5
X
X
A4 A5
X
X
A4 A5
X
X
A4
A5
X
X
A4
A5
X
X
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