TMS320C5505AZCH10 其他数据使用手册 - TI（德州仪器）

This section describes the usage notes and advisories that apply to silicon revision 2.0 of the

TMS320C5505 and TMS320C5504 devices.

Usage notes highlight and describe particular situations where the device's behavior may not match

presumed or documented behavior. This may include behaviors that affect device performance or

functional correctness. These usage notes will be incorporated into future documentation updates for the

• Hardware reset being asserted ( RESET = low)

• An enabled RTC alarm or periodic interrupt occurring

• The INT0 or INT1 pins being asserted (low) (level-sensitive)

• The WAKEUP pin being asserted (high) (level-sensitive)

When the master clock is disabled, there are no clocks for edge detection and therefore the INT0, INT1,

and WAKEUP pins are level-sensitive. This means that a low on either the INT0 or INT1 or a high on the

WAKEUP pin will force bit 15 of the PCGCR register to "0", enabling the master clock. Attempting to write

a "1" to bit 15 of the PCGCR register while INT0, INT1, or WAKEUP are asserted will be unsuccessful

since re-enabling the clocks has a higher priority than disabling them.

When the WAKEUP pin is configured as an output-pin, the WAKEUP pin only functions as a GPO and no

For proper C550x device operation on silicon revision 2.0, the "RESERVED" bits in the RTCOSC register

(0x192C) should always be set to "zero".