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TMS320C6745DPTPT3 其他数据使用手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
LQFP-176
描述:
TMS320C6745 ， TMS320C6747固定/浮点数字信号处理器 TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor
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技术参数、封装参数在P5P6P8P9P10P11P12P13P14P15P16P17
应用领域在P45
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TMS320C6745DPTPT3数据手册
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Silicon Revision 3.0 Usage Notes and Known Design Exceptions to Functional Specifications
2 Silicon Revision 3.0 Usage Notes and Known Design Exceptions to Functional
Specifications
This section describes the usage notes and advisories that apply to silicon revision 3.0 of the device.
2.1 Usage Notes for Silicon Revision 3.0
Usage notes highlight and describe particular situations where the device's behavior may not match
presumed or documented behavior. This may include behaviors that affect device performance or
functional correctness. These usage notes will be incorporated into future documentation updates for the
device (such as the device-specific data sheet), and the behaviors they describe will not be altered in
future silicon revisions.
2.1.1 McASP: Inactive Slot Usage Note
On all the silicon revisions, McASP underflow (underruns) can occurs if any of the McASP serialzer is
configured as a transmit serializer with any of the time slot-n in XTDM register field is set to inactive and
EDMA is used to do the transfers. This is independent of whether the EDMA/CPU transfers are through
peripheral configuration bus or the DMA port.
If the EDMA is used to service the McASP with any of the time slot-n in XTDM register field is set to
inactive, EDMA may not be triggered upon enabling serializer and hence data transfer will be stalled or if
data transfer has begun with some random value and goes to underrun errors, that breaks the data
transfer operation.
To ensure proper McASP (transmit) data transfer either through config or EDMA port, ensure the time slot-
n in XTDM register field is set to active. For example, if a serializer is configured for transmit operation
with a 5-slot TDM frame in which it is only required to transmit data in slots 0 to 2, but make sure all five
slots (0 to 4) should be configured as active. The EDMA configuration and user application should account
for the transfer of irrelevant data to the McASP for slots 3 and 4.
2.1.2 USB0: Generic RNDIS Usage Note
On all silicon revisions, when using Generic RNDIS mode, the user should ensure that the DMA
configuration has completed prior to the host starting a transfer. This condition is sometimes violated when
performing back-to-back data transfers (not transactions). If a new transfer is scheduled by a host while
the device is working on the previous transfer and the data transfer size for the new transfer is different
than the previous transfer data size, then there exists a contention between the two transfer sizes creating
undesired behavior resulting with a DMA lock up. A case in point where this violation could happen is
demonstrated by the example below.
A user configures the DMA in Generic RNDIS mode expecting a data size of 512 bytes or less from a
host. The host sends 512 bytes or less of data to the device. While the device is in the process of working
on the received data to figure out the size of the next data transfer, the host starts a new data transfer
addressing the same endpoint. Since the endpoint FIFO is empty, the device accepts the data and the
DMA starts to transfer the received data from the receive FIFO to memory. At the same time, the
application on the device side finishes and figures out the next transfer data size (using the data received
from previous transfer) and reconfigures the Generic DMA Size register for the second transfer. If the
second transfer size is different from the first transfer size, the contention happens at this point. The host
has already started the second transfer prior to the device re-configuring the DMA parameters. The
application on the device side, updates the DMA size register content for the second transfer while the
DMA is in the middle of the second transfer using the DMA size register content of the first transfer. This
effectively results with altering the DMA size register content while the DMA is in the middle of a transfer.
Changing DMA parameters while in the middle of a transfer is not allowed and when done it will create
undesirable outcomes.
Workaround: This is not a bug and for this reason, there exists no workaround. This is a caution for the
user to be aware of this issue and hence to ensure that this scenario is avoided. If there exists an idle time
in between the two back-to-back transfers, this issue will not exist. When expecting a back-to-back
transfer where RNDIS mode can not be used, the user needs to use TRANSPARENT mode. When using
TRANSPARENT mode, the application will be receiving more interrupts, that is, interrupts will be
generated on each USB packets as opposed to receiving a single interrupt on the completion of a transfer.
5
SPRZ253G–May 2009–Revised June 2014 TMS320C6745 Silicon Revisions 3.0, 2.1, 2.0, 1.1, and 1.0
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