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TMS320C6748AZWT3 其他数据使用手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
LFBGA-361
描述:
固定/浮点DSP Fixed/Floating-Point DSP
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标记信息在P3
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技术参数、封装参数在P4P5P6P7P9P10P11P12P13P14P15P16
应用领域在P56
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TMS320C6748AZWT3数据手册
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Silicon Revision 2.3 Usage Notes and Known Design Exceptions to Functional Specifications
www.ti.com
In addition to using an external clock source, several other board and software recommendations specific
to this device can improve system-level ESD immunity:
• The OSCIN and OSCVSS (and OSCOUT, if used) should be routed as short as possible to reduce
their ability to pick up EMI noise.
• Route the OSCIN signal on inner board layers where it is shield by power and ground planes.
• Disable the DLL REFCLK signal in the DDR EMIF PHY. This prevents the DLL used by the DDR PHY
from dynamically tracking glitches on the input clock. This can be done after normal DDR initialization
by setting the following bit in the DDR PHY Control Register (0xB00000E4):
// Configure DDR PLL
Set_DDRPLL_150MHz();
// Configure DDR timings
DEVICE_DDR2Config(150);
// Minimum 600 MCLK cycle delay (allow master DLL to lock)
Delay_600();
// Perform dummy DDR read
volatile unsigned int k=0;
...
k = *(volatile unsigned int*) (0xC0000000);
// Disable DLL REFCLK
DRPYC1R |= 0x00002000;
• The processor should be provided as much power supply decoupling as is practical and placed as
close to the processor as possible.
• Follow the entire DDR interface implementation requirements in the device datasheet.
• Implement the PLL filtering circuits shown in the device datasheet.
These recommendations are in addition to standard methods for increasing system ESD immunity, such
as using shielding enclosures, proper grounding and PCB stackup, and ESD protection circuitry.
6
TMS320C6748 Fixed- and Floating-Point DSP Silicon Revisions 2.3, 2.1, 2.0, SPRZ303H–June 2009–Revised March 2014
1.1 and 1.0
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