Datasheet 搜索 > FPGA芯片 > Altera（阿尔特拉） > 5CSEBA4U19C6N 数据手册 > 5CSEBA4U19C6N 产品设计参考手册 4/6 页
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5CSEBA4U19C6N 产品设计参考手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
BGA-484
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5CSEBA4U19C6N数据手册
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若手册格式错乱，请下载阅览PDF原文件
CvP is supported if the fourth alphanumeric character from the left (“Z” in Figure below) is equal to, or
later in the alphabet than the letter in the "Revision with Fix" column of the table shown in the "Status"
section below.
Figure 2: Altera Date Code Marking Format
This figure explains the date code and revision marking format.
A X β Z ## #####
Die Revision
Status
Affects: Cyclone V GX and GT devices, except for 5CGXC3
Status: Devices that are CvP capable will be available in Q2 2013
The table below shows which revisions will have the fix.
Table 3: Device and Die Revisions
Note:
Future revisions beyond the one listed in the "Revision with Fix" column will be CvP capable.
Member Code Revisions without Fix Revision with Fix
5CGXC3 None A
5CGXC4 A B
5CGXC5 A B
5CGXC7 A and B C
5CGXC9 A B
5CGTD5 A B
5CGTD7 A and B C
5CGTD9 A B
Note: For Gen2 CvP updates or further inquiries, please contact mySupport.
Usermode High Icc
Description
When the affected device transitions into User mode, high Icc is observed, due to internal dataline
contention.
4
Usermode High Icc
ES-1035
2015.09.18
Altera Corporation
Cyclone V GX, GT, and E Device Errata
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