ADC08038BIWM 产品设计参考手册 - TI（德州仪器）

Note 4: When the input voltage V

at any pin exceeds the power supplies (V

< (AGND or DGND) or V

) the current at that pin should be limited to 5

mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four

pins.

Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T

, θ

and the ambient temperature, T

. The maximum

allowable power dissipation at any temperature is P

− T

)/θ

or the number given in the Absolute Maximum Ratings, whichever is lower. For these

devices, T

= 125°C. The typical thermal resistances (θ

Note 8: Typical figures are at T

Note 9: Guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 10: Total unadjusted error includes offset, full-scale, linearity, multiplexer.

Note 11: Cannot be tested for the ADC08032.

Note 12: For V

≥ V

the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct

for analog input voltages one diode drop below ground or one diode drop greater than V

supply. During testing at low V

inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures, which will cause errors for analog inputs near full-scale. The spec

Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following

two cases are considered: one, with the selected channel tied high (5 V

) and the remaining seven off channels tied low (0 V

off channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured.

The two cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.

Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these

limits the minimum time the clock is high or low must be at least 450 ns. The maximum time the clock can be high or low is 100 μs.

Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to

allow for comparator response time.

Note 16: For the ADC08032 V