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CC2511F32RSPR 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
RF射频器件
封装:
QFN-36
描述:
低功耗的SoC （系统级芯片）与MCU，存储器， 2.4 GHz射频收发器和USB控制器 Low-Power SoC (System-on-Chip) with MCU, Memory, 2.4 GHz RF Transceiver, and USB Controller
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P7P8Hot
原理图在P4P131P132P138P140P141
封装尺寸在P219
标记信息在P219P220
封装信息在P3P218P219P220
功能描述在P185
技术参数、封装参数在P80P81P82P83P84P85P86P87P88P89P90P91
应用领域在P2P223
电气规格在P85P86P94P95P96P103P104
型号编号列表在P80P81
导航目录
CC2511F32RSPR数据手册
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AM3517, AM3505
SPRS550F –OCTOBER 2009–REVISED JULY 2014
www.ti.com
– Supports Both Integer and Floating-Point SIMD – 16- and 32-Bit Memory Controller with 1GB of
Total Address Space
– Jazelle
®
RCT Execution Environment
Architecture – Double Data Rate (DDR2) SDRAM, Mobile
Double Data Rate (mDDR)SDRAM
– Dynamic Branch Prediction with Branch Target
Address Cache, Global History Buffer and 8- – SDRAM Memory Scheduler (SMS) and Rotation
Entry Return Stack Engine
– Embedded Trace Macrocell [ETM] Support for • General Purpose Memory Controller (GPMC)
Noninvasive Debug
– 16-Bit-Wide Multiplexed Address/Data Bus
– 16KB of Instruction Cache (4-Way Set-
– Up to 8 Chip-Select Pins with 128MB of
Associative)
Address Space per Chip-Select Pin
– 16KB of Data Cache (4-Way Set-Associative)
– Glueless Interface to NOR Flash, NAND Flash
– 256KB of L2 Cache (with ECC Hamming Code Calculation), SRAM
and Pseudo-SRAM
• PowerVR SGX™ Graphics Accelerator (AM3517
Only) – Flexible Asynchronous Protocol Control for
Interface to Custom Logic (FPGA, CPLD,
– Tile-Based Architecture Delivering up to 10
ASICs, and so forth)
MPoly/sec
– Nonmultiplexed Address/Data Mode (Limited 2-
– Universal Scalable Shader Engine: Multi-
KB Address Space)
threaded Engine Incorporating Pixel and Vertex
Shader Functionality • Test Interfaces
– Industry Standard API Support: OpenGLES 1.1 – IEEE-1149.1 (JTAG) Boundary-Scan
and 2.0, OpenVG1.0 Compatible
– Fine-Grained Task Switching, Load Balancing, – Embedded Trace Macro Interface (ETM)
and Power Management
• 65-nm CMOS Technology
– Programmable, High-Quality Image Anti-Aliasing
• Packages:
• Endianess
– 491-Pin BGA (17 x 17, 0.65-mm Pitch)
– ARM Instructions – Little Endian [ZCN Suffix]
with Via Channel™ Array Technology
– ARM Data – Configurable
– 484-Pin PBGA (23 x 23, 1-mm Pitch)
• SDRC Memory Controller
[ZER Suffix]
1.2 Applications
• Single-Board Computers • Transportation
• Industrial and Home Automation • Navigation
• Digital Signage • Smart White Goods
• Point of Service • Digital TV
• Portable Media Player • Digital Video Camera
• Portable Industrial • Gaming
2 Device Summary Copyright © 2009–2014, Texas Instruments Incorporated
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Product Folder Links: AM3517 AM3505
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