Datasheet 搜索 > FPGA芯片 > Altera（阿尔特拉） > EP1S30F1020C7N 数据手册 > EP1S30F1020C7N 产品设计参考手册 4/292 页
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EP1S30F1020C7N 产品设计参考手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
FBGA-1020
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P101P102P287Hot
典型应用电路图在P30P32P34P36P287P292
原理图在P26P79P80P287P289
封装尺寸在P285
型号编码规则在P7P285P286P292
封装信息在P286P292
功能描述在P25P26P287
技术参数、封装参数在P13P181P183P184P186P187P188P189P190P191P192P193
应用领域在P200P201
电气规格在P178P292
导航目录
EP1S30F1020C7N数据手册
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iv Altera Corporation
Contents Stratix Device Handbook, Volume 1
DSP Block Interface ........................................................................................................................ 2–70
PLLs & Clock Networks ..................................................................................................................... 2–73
Global & Hierarchical Clocking ................................................................................................... 2–73
Enhanced & Fast PLLs ................................................................................................................... 2–81
Enhanced PLLs ............................................................................................................................... 2–87
Fast PLLs ........................................................................................................................................ 2–100
I/O Structure ...................................................................................................................................... 2–104
Double-Data Rate I/O Pins ......................................................................................................... 2–111
External RAM Interfacing ........................................................................................................... 2–115
Programmable Drive Strength ................................................................................................... 2–119
Open-Drain Output ...................................................................................................................... 2–120
Slew-Rate Control ........................................................................................................................ 2–120
Bus Hold ........................................................................................................................................ 2–121
Programmable Pull-Up Resistor ................................................................................................ 2–122
Advanced I/O Standard Support .............................................................................................. 2–122
Differential On-Chip Termination ............................................................................................. 2–127
MultiVolt I/O Interface ............................................................................................................... 2–129
High-Speed Differential I/O Support ............................................................................................ 2–130
Dedicated Circuitry ...................................................................................................................... 2–137
Byte Alignment ............................................................................................................................. 2–140
Power Sequencing & Hot Socketing ............................................................................................... 2–140
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3–1
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–5
Configuration ......................................................................................................................................... 3–5
Operating Modes .............................................................................................................................. 3–5
Configuring Stratix FPGAs with JRunner .................................................................................... 3–7
Configuration Schemes ................................................................................................................... 3–7
Partial Reconfiguration .................................................................................................................... 3–7
Remote Update Configuration Modes .......................................................................................... 3–8
Stratix Automated Single Event Upset (SEU) Detection ................................................................ 3–12
Custom-Built Circuitry .................................................................................................................. 3–13
Software Interface ........................................................................................................................... 3–13
Temperature Sensing Diode ............................................................................................................... 3–13
Chapter 4. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 4–1
Power Consumption ........................................................................................................................... 4–17
Timing Model ....................................................................................................................................... 4–19
Preliminary & Final Timing .......................................................................................................... 4–19
Performance .................................................................................................................................... 4–20
Internal Timing Parameters .......................................................................................................... 4–22
External Timing Parameters ......................................................................................................... 4–33
Stratix External I/O Timing .......................................................................................................... 4–36
I/O Timing Measurement Methodology .................................................................................... 4–60
External I/O Delay Parameters .................................................................................................... 4–66
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