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EP2C20F256C7 产品设计参考手册 - Intel（英特尔）
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EP2C20F256C7数据手册
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Virtual JTAG Intel
®
FPGA IP Core User Guide
The Virtual JTAG Intel
®
FPGA IP core provides access to the PLD source through the
JTAG interface. This IP core is optimized for Intel device architectures. Using IP cores
in place of coding your own logic saves valuable design time, and offers more efficient
logic synthesis and device implementation. You can scale the IP core's size by setting
parameters.
Related Information
Introduction to Intel FPGA IP Cores
Introduction
The Virtual JTAG Intel FPGA IP core allows you to create your own software solution
for monitoring, updating, and debugging designs through the JTAG port without using
I/O pins on the device, and is one feature in the On-Chip Debugging Tool Suite. The
Intel Quartus
®
Prime software or JTAG control host identifies each instance of this IP
core by a unique index. Each IP core instance functions in a flow that resembles the
JTAG operation of a device. The logic that uses this interface must maintain the
continuity of the JTAG chain on behalf the PLD device when this instance becomes
active.
With the Virtual JTAG Intel FPGA IP core you can build your design for efficient, fast,
and productive debugging solutions. Debugging solutions can be part of an evaluation
test where you use other logic analyzers to debug your design, or as part of a
production test where you do not have a host running an embedded logic analyzer. In
addition to debugging features, you can use the Virtual JTAG Intel FPGA IP core to
provide a single channel or multiple serial channels through the JTAG port of the
device. You can use serial channels in applications to capture data or to force data to
various parts of your logic.
Each feature in the On-Chip Debugging Tool Suite leverages on-chip resources to
achieve real time visibility to the logic under test. During runtime, each tool shares the
JTAG connection to transmit collected test data to the Intel Quartus Prime software for
analysis. The tool set consists of a set of GUIs, IP core intellectual property (IP) cores,
and Tcl application programming interfaces (APIs). The GUIs provide the configuration
of test signals and the visualization of data captured during debugging. The Tcl
scripting interface provides automation during runtime.
The Virtual JTAG Intel FPGA IP core provides you direct access to the JTAG control
signals routed to the FPGA core logic, which gives you a fine granularity of control
over the JTAG resource and opens up the JTAG resource as a general-purpose serial
communication interface. A complete Tcl API is available for sending and receiving
UG-SLDVRTL | 2020.12.01
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