Datasheet 搜索 > FPGA芯片 > Altera（阿尔特拉） > EP2S60F672C5 数据手册 > EP2S60F672C5 产品设计参考手册 5/50 页
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EP2S60F672C5 产品设计参考手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
FBGA-672
描述:
FPGA - 现场可编程门阵列 FPGA - Stratix II 3022 LABs 492 IOs
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P20
功能描述在P44
应用领域在P7P12
导航目录
EP2S60F672C5数据手册
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Version columns update when upgrade is complete. Example designs provided with any Altera IP core
regenerate automatically whenever you upgrade an IP core.
3. To manually upgrade an individual IP core, select the IP core and then click Upgrade in Editor (or
simply double-click the IP core name. The parameter editor opens, allowing you to adjust parameters
and regenerate the latest version of the IP core.
Figure 3: Upgrading IP Cores
Runs “Auto Upgrade” on all supported outdated cores
Opens editor for manual IP upgrade
“Auto Upgrade”
supported
Upgrade required
Upgrade details
“Auto Upgrade”
successful
Note: IP cores older than software version 12.0 do not support upgrade. Altera verifies that the
current version of the software compiles the previous version of each IP core. The Altera IP
Release Notes reports any verification exceptions for Altera IP cores. Altera does not verify
compilation for IP cores older than the previous two releases.
Related Information
Altera IP Release Notes
UG-SLDVRTL
2015.11.20
Upgrading IP Cores
5
Altera Virtual JTAG (altera_virtual_jtag) IP Core User Guide
Altera Corporation
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