Datasheet 搜索 > 32位控制器 > NXP（恩智浦） > LPC1343FBD48 数据手册 > LPC1343FBD48 产品设计参考手册 5/370 页
器件3D模型￥ 19.685
LPC1343FBD48 产品设计参考手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
32位控制器
封装:
LQFP
描述:
NXP LPC1343FBD48 微控制器, 32位, ARM 皮质-M3, 72 MHz, 32 KB, 8 KB, 48 引脚, LQFP
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P13P120P121P122P123P124P125P126P127P128P129P130Hot
原理图在P8P305
型号编码规则在P6
功能描述在P55P88P137P140P142P152P164P165P200P209P252P260
应用领域在P209P229P232P235P236P239P241P268P282P301P307P353
导航目录
LPC1343FBD48数据手册
Page:
of 370 Go
若手册格式错乱，请下载阅览PDF原文件
UM10375 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
User manual Rev. 5 — 21 June 2012 5 of 370
NXP Semiconductors
UM10375
Chapter 1: LPC13xx Introductory information
– USB 2.0 full-speed device controller with on-chip PHY for device (LPC1342/43
only).
– UART with fractional baud rate generation, modem, internal FIFO, and
RS-485/EIA-485 support.
– SSP controller with FIFO and multi-protocol capabilities.
– Additional SSP controller on LPC1313FBD48/01.
– I
2
C-bus interface supporting full I
2
C-bus specification and Fast-mode Plus with a
data rate of 1 Mbit/s with multiple address recognition and monitor mode.
• Other peripherals:
– Up to 42 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors.
– Four general purpose counter/timers with a total of four capture inputs and 13
match outputs.
– Programmable WatchDog Timer (WDT).
– Programmable Windowed Watchdog Timer (WWDT) on LPC1311/01 and
LPC1313/01.
– System tick timer.
• Serial Wire Debug and Serial Wire Trace port.
• High-current output driver (20 mA) on one pin.
• High-current sink drivers (20 mA) on two I
2
C-bus pins in Fast-mode Plus.
• Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, and Deep power-down modes.
• Power profiles residing in boot ROM allowing to optimize performance and minimize
power consumption for any given application through one simple function call.
(LPC1300L series, on LPC1311/01 and LPC1313/01 only.)
• Three reduced power modes: Sleep, Deep-sleep, and Deep power-down.
• Single power supply (2.0 V to 3.6 V).
• 10-bit ADC with input multiplexing among 8 pins.
• GPIO pins can be used as edge and level sensitive interrupt sources.
• Clock output function with divider that can reflect the system oscillator clock, IRC
clock, CPU clock, or the watchdog clock.
• Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40
of the functional pins.
• Brownout detect with four separate thresholds for interrupt and one threshold for
forced reset (four thresholds for forced reset on the LPC1311/01 and LPC1313/01
parts).
• Power-On Reset (POR).
• Integrated oscillator with an operating range of 1 MHz to 25 MHz.
• 12 MHz internal RC oscillator trimmed to 1 % accuracy over the entire temperature
and voltage range that can optionally be used as a system clock.
• Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
