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P2010NXN2KHC 产品设计参考手册 - NXP（恩智浦）
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Freescale Semiconductor
Application Note
© Freescale Semiconductor, Inc., 2005, 2007. All rights reserved.
The design guidelines presented in this document apply to
products that leverage the DDR2 SDRAM IP core, and they
are based on a compilation of internal platforms designed by
Freescale Semiconductor, Inc. The purpose of these
guidelines is to minimize board-related issues across
multiple memory topologies while allowing maximum
flexibility for the board designer.
Because numerous memory topologies and interface
frequencies are possible on the DDR2 SDRAM interface,
Freescale highly recommends that the system/board designer
verify all design aspects (signal integrity, electrical timings,
and so on) through simulation before PCB fabrication.
Document Number: AN2910
Rev. 2, 03/2007
Contents
1 Designer’s Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Termination Dissipation. . . . . . . . . . . . . . . . . . . . . . . . 7
3 VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 VTT Voltage Rail. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Layout Guidelines for the Signal Groups . . . . . . . . . . .8
5.1 Data—MDQ[0:63], MDQS[0:8], MDM[0:8],
MECC[0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
5.2 Layout Recommendations . . . . . . . . . . . . . . . . . . .9
6 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
7 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
8 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Hardware and Layout Design
Considerations for DDR2 SDRAM
Memory Interfaces
by DSD Applications
Freescale Semiconductor, Inc.
Austin, TX
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