Datasheet 搜索 > 微控制器 > ST Microelectronics（意法半导体） > STM32F101R6T6A 数据手册 > STM32F101R6T6A 产品设计参考手册 5/31 页
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STM32F101R6T6A 产品设计参考手册 - ST Microelectronics（意法半导体）
制造商:
ST Microelectronics（意法半导体）
分类:
微控制器
封装:
LQFP-64
描述:
STMICROELECTRONICS STM32F101R6T6A 微控制器, 32位, ARM 皮质-M3, 36 MHz, 32 KB, 6 KB, 64 引脚, LQFP
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STM32F101R6T6A数据手册
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PM0075
Doc ID 17863 Rev 2 5/31
Glossary
This section gives a brief definition of acronyms and abbreviations used in this document:
● Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes.
● Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx
microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes.
● High-density devices are STM32F101xx and STM32F103xx microcontrollers where
the Flash memory density ranges between 256 and 512 Kbytes.
● Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
● The Cortex-M3 core integrates two debug ports:
– JTAG debug port (JTAG-DP) provides a 5-pin standard interface based on the
Joint Test Action Group (JTAG) protocol.
– SWD debug port (SWD-DP) provides a 2-pin (clock and data) interface based on
the Serial Wire Debug (SWD) protocol.
For both the JTAG and SWD protocols please refer to the Cortex M3 Technical
Reference Manual
● Word: data/instruction of 32-bit length
● Half word: data/instruction of 16-bit length
● Byte: data of 8-bit length
● FPEC (Flash memory program/erase controller): write operations to the main memory
and the information block are managed by an embedded Flash program/erase
controller (FPEC).
● IAP (in-application programming): IAP is the ability to re-program the Flash memory of
a microcontroller while the user program is running.
● ICP (in-circuit programming): ICP is the ability to program the Flash memory of a
microcontroller using the JTAG protocol, the SWD protocol or the boot loader while the
device is mounted on the user application board.
● I-Code: this bus connects the Instruction bus of the Cortex-M3 core to the Flash
instruction interface. Prefetch is performed on this bus.
● D-Code: this bus connects the D-Code bus (literal load and debug access) of the
Cortex-M3 to the Flash Data Interface.
● Option bytes: product configuration bits stored in the Flash memory
● OBL: option byte loader.
● AHB: advanced high-performance bus.
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