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TMS320C5515 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
封装:
NFBGA-196
描述:
定点数字信号处理器
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P14P58P61Hot
典型应用电路图在P135
原理图在P4
封装尺寸在P156
标记信息在P156
封装信息在P155P156P157
功能描述在P57
技术参数、封装参数在P11P67P72P73P74P75P76P77P78P79P80P81
应用领域在P2P159
电气规格在P11P37P42P65P69P70P71P72P73P74P75P76
导航目录
TMS320C5515数据手册
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若手册格式错乱，请下载阅览PDF原文件
TMS320C5515
www.ti.com
SPRS645F –AUGUST 2010–REVISED OCTOBER 2013
TMS320C5515 Fixed-Point Digital Signal Processor
Check for Samples: TMS320C5515
1 Fixed-Point Digital Signal Processor
1.1 Features
12
• High-Performance, Low-Power, TMS320C55x™ • Universal Asynchronous Receiver/Transmitter
Fixed-Point Digital Signal Processor (UART)
– 16.67-, 13.33-, 10-, 8.33-ns Instruction Cycle • Serial-Port Interface (SPI) With Four Chip-
Time Selects
– 60-, 75-, 100-, 120-MHz Clock Rate • Master/Slave Inter-Integrated Circuit (I
2
C Bus™)
– One/Two Instructions Executed per Cycle • Four Inter-IC Sound (I
2
S Bus™) for Data
Transport
– Dual Multipliers [Up to 200 or 240 Million
Multiply-Accumulates per Second (MMACS)] • Device USB Port With Integrated 2.0 High-
Speed PHY that Supports:
– Two Arithmetic/Logic Units (ALUs)
– USB 2.0 Full- and High-Speed Device
– Three Internal Data/Operand Read Buses
and Two Internal Data/Operand Write Buses • LCD Bridge With Asynchronous Interface
– Software-Compatible With C55x Devices • Tightly-Coupled FFT Hardware Accelerator
– Industrial Temperature Devices Available • 10-Bit 4-Input Successive Approximation (SAR)
ADC
• 320K Bytes Zero-Wait State On-Chip RAM,
Composed of: • Real-Time Clock (RTC) With Crystal Input, With
Separate Clock Domain and Power Supply
– 64K Bytes of Dual-Access RAM (DARAM),
8 Blocks of 4K x 16-Bit • Four Core Isolated Power Supply Domains:
Analog, RTC, CPU and Peripherals, and USB
– 256K Bytes of Single-Access RAM (SARAM),
32 Blocks of 4K x 16-Bit • Four I/O Isolated Power Supply Domains: RTC
I/O, EMIF I/O, USB PHY, and DV
DDIO
• 128K Bytes of Zero Wait-State On-Chip ROM
(4 Blocks of 16K x 16-Bit) • Three integrated LDOs (DSP_LDO, ANA_LDO,
and USB_LDO) to power the isolated domains:
• 4M x 16-Bit Maximum Addressable External
DSP Core, Analog, and USB Core, respectively
Memory Space (SDRAM/mSDRAM)
• Low-Power S/W Programmable Phase-Locked
• 16-/8-Bit External Memory Interface (EMIF) with
Loop (PLL) Clock Generator
Glueless Interface to:
• On-Chip ROM Bootloader (RBL) to Boot From
– 8-/16-Bit NAND Flash, 1- and 4-Bit ECC
NAND Flash, NOR Flash, SPI EEPROM, SPI
– 8-/16-Bit NOR Flash
Serial Flash or I2C EEPROM
– Asynchronous Static RAM (SRAM)
• IEEE-1149.1 (JTAG)
– SDRAM/mSDRAM (1.8-, 2.5-, 2.75-, and 3.3-V)
Boundary-Scan-Compatible
• Direct Memory Access (DMA) Controller
• Up to 26 General-Purpose I/O (GPIO) Pins
– Four DMA With 4 Channels Each (16-
(Multiplexed With Other Device Functions)
Channels Total)
• 196-Terminal Pb-Free Plastic BGA (Ball Grid
• Three 32-Bit General-Purpose Timers
Array) (ZCH Suffix)
– One Selectable as a Watchdog and/or GP
• 1.05-V Core (60 or 75 MHz), 1.8-V, 2.5-V, 2.75-V,
• Two MultiMedia Card/Secure Digital (MMC/SD)
or 3.3-V I/Os
Interfaces
• 1.3-V Core (100, 120 MHz), 1.8-V, 2.5-V, 2.75-V,
or 3.3-V I/Os
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2010–2013, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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