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TMS320C6455BZTZ 产品设计参考手册 - TI(德州仪器)
制造商:
TI(德州仪器)
分类:
DSP数字信号处理器
封装:
FCBGA-697
描述:
定点数字信号处理器 Fixed-Point Digital Signal Processor
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P16Hot
原理图在P4P79P83P147P170
封装尺寸在P250P251P252
标记信息在P250P251P252
封装信息在P249P250P251P252P253
功能描述在P55P56P57
技术参数、封装参数在P97P101P102P103P104P105P106P107P108P109P110P111
应用领域在P215P257
电气规格在P74P99P100P101P102P103P104P105P106P107P108P109
型号编号列表在P8
导航目录
TMS320C6455BZTZ数据手册
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TMS320C6455
www.ti.com
SPRS276M –MAY 2005–REVISED MARCH 2012
TMS320C6455 Fixed-Point Digital Signal Processor
Check for Samples: TMS320C6455
1 Features
12
– 1.25-, 2.5-, 3.125-Gbps Link Rates
• High-Performance Fixed-Point DSP (C6455)
– Message Passing, DirectIO Support, Error
– 1.39-, 1.17-, 1-, 0.83-ns Instruction Cycle
Mgmt Extensions, Congestion Control
Time
– IEEE 1149.6 Compliant I/Os
– 720-MHz, 850-MHz, 1-GHz, 1.2-GHz Clock
Rate • DDR2 Memory Controller
– Eight 32-Bit Instructions/Cycle – Interfaces to DDR2-533 SDRAM
– 9600 MIPS/MMACS (16-Bits) – 32-Bit/16-Bit, 533-MHz (data rate) Bus
– Commercial Temperature [0°C to 90°C] – 512M-Byte Total Addressable External
Memory Space
– Extended Temperature [-40°C to 105°C]
• EDMA3 Controller (64 Independent Channels)
• TMS320C64x+™ DSP Core
• 32-/16-Bit Host-Port Interface (HPI)
– Dedicated SPLOOP Instruction
• 32-Bit 33-/66-MHz, 3.3-V Peripheral Component
– Compact Instructions (16-Bit)
Interconnect (PCI) Master/Slave Interface
– Instruction Set Enhancements
Conforms to PCI Local Bus Specification (v2.3)
– Exception Handling
• One Inter-Integrated Circuit (I
2
C) Bus
• TMS320C64x+ Megamodule L1/L2 Memory
• Two McBSPs
Architecture:
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– 256K-Bit (32K-Byte) L1P Program Cache
– IEEE 802.3 Compliant
[Direct Mapped]
– Supports Multiple Media Independent
– 256K-Bit (32K-Byte) L1D Data Cache
Interfaces (MII, GMII, RMII, and RGMII)
[2-Way Set-Associative]
– 8 Independent Transmit (TX) and
– 16M-Bit (2048K-Byte) L2 Unified Mapped
8 Independent Receive (RX) Channels
RAM/Cache [Flexible Allocation]
• Two 64-Bit General-Purpose Timers,
– 256K-Bit (32K-Byte) L2 ROM
Configurable as Four 32-Bit Timers
– Time Stamp Counter
• UTOPIA
• Enhanced Viterbi Decoder Coprocessor (VCP2)
– UTOPIA Level 2 Slave ATM Controller
– Supports Over 694 7.95-Kbps AMR
– 8-Bit Transmit and Receive Operations up to
– Programmable Code Parameters
50 MHz per Direction
• Enhanced Turbo Decoder Coprocessor (TCP2)
– User-Defined Cell Format up to 64 Bytes
– Supports up to Eight 2-Mbps 3GPP
• 16 General-Purpose I/O (GPIO) Pins
(6 Iterations)
• System PLL and PLL Controller
– Programmable Turbo Code and Decoding
• Secondary PLL and PLL Controller, Dedicated
Parameters
to EMAC and DDR2 Memory Controller
• Endianess: Little Endian, Big Endian
• Advanced Event Triggering (AET) Compatible
• 64-Bit External Memory Interface (EMIFA)
• Trace-Enabled Device
– Glueless Interface to Asynchronous
• IEEE-1149.1 (JTAG™) Boundary-Scan-
Memories (SRAM, Flash, and EEPROM) and
Compatible
Synchronous Memories (SBSRAM, ZBT
SRAM) • 697-Pin Ball Grid Array (BGA) Package
(CTZ, GTZ, or ZTZ Suffix), 0.8-mm Ball Pitch
– Supports Interface to Standard Sync Devices
and Custom Logic • 0.09-μm/7-Level Cu Metal Process (CMOS)
(FPGA, CPLD, ASICs, etc.)
• 3.3-/1.8-/1.5-/1.25-/1.2-V I/Os,
– 32M-Byte Total Addressable External 1.25-/1.2-V Internal
Memory Space
• Four 1x Serial RapidIO® Links (or One 4x),
v1.2 Compliant
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2005–2012, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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