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TMS320C6474FCUN 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
BFBGA-561
描述:
TMS320C6474多核数字信号处理器 TMS320C6474 Multicore Digital Signal Processor
Pictures:
3D模型
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焊盘图
引脚图
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引脚图在P17Hot
原理图在P5P53P56P58P130P136P160
封装尺寸在P209P210
标记信息在P209P210
封装信息在P208P209P210P211
功能描述在P1P45
技术参数、封装参数在P72P74P75P76P77P78P79P80P81P82P83P84
应用领域在P157P215
电气规格在P73P74P75P76P77P78P79P80P81P82P83P84
型号编号列表在P9
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TMS320C6474FCUN数据手册
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TMS320C6474
www.ti.com
SPRS552H–OCTOBER 2008– REVISED APRIL 2011
1.2 Description
The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore
DSP generation in the TMS320C6000™ DSP platform.
The C6474 device is based on the third-generation high-performance, advanced VelociTI™
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).
The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™
DSP platform.
1.2.1 Core Processor
Based on 65-nm process technology and 3.6 GHz of total raw DSP processing power with performance of
up to 28,800 million instructions per second (MIPS) [or 28,800 16-bit MMACs per cycle], the C6474 device
offers cost-effective solutions to high-performance DSP programming challenges with three independent
DSP subsystems. The DSP possesses the operational flexibility of high-speed controllers and numerical
capability of array processors.
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier
C6000 devices, two of these functional units are multipliers or .M units. Each C64x+ .M unit doubles the
multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs)
every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At
a1.2-GHz rate, this means 9600 16-bit MMACs can occur every microsecond. Moreover, each multiplier
on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.
The C6474 DSP integrates a large amount of on-chip memory organized as a three-level memory system.
The level-1 data memories on the device are 32 KB each. This memory can be configured as mapped
RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a
direct-mapped cache where as L1 data (L1D) is a two-way set associative cache. The level-3 (L3) ROM is
64 KB in the device. The C64x+ megamodule also has a 32-bit peripheral configuration (CFG) port, an
internal DMA (IDMA) controller, a system component with reset/boot control, and a free-running 32-bit
timer for time stamp.
The C64x+ DSP core has a complete set of development tools which includes: a new C compiler, an
assembly optimizer to simplify programming and scheduling, and a Windows
®
debugger interface for
visibility into source code execution.
The DMA switch fabric provides enhanced on-chip connectivity between the DSP cores and the
peripherals and accelerators.
1.2.2 Peripherals
The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial
ports (McBSPs) each at 100 Mbps; six 64-bit general-purpose timers (also configurable as twelve 32-bit
timers); 16 general-purpose input/output ports (GPIO) with programmable interrupt/event generation
modes; a 1000-Mbps Ethernet media access controller (EMAC), which provides an efficient interface
between the C6474 DSP core processor and the network; a management data input/output (MDIO)
module (also part of EMAC), which controls PHY configuration and status monitoring; a frame
synchronization (FSYNC) module, which synchronizes DMA transactions; a semaphore hardware block
(Semaphore), which allows access to shared resources with unique interrupts to each of the cores to
identify when that core has acquired the resource; and a 16-/32-bit DDR2 SDRAM interface.
The I2C port allows the DSP to easily control peripheral devices and communicate with a host processor.
Copyright © 2008–2011, Texas Instruments Incorporated Features 3
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