Datasheet 搜索 > DSP数字信号处理器 > TI（德州仪器） > TMS320C6678ACYPA 数据手册 > TMS320C6678ACYPA 产品设计参考手册 1/247 页
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TMS320C6678ACYPA 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
FCBGA-841
描述:
多核固定和浮点数字信号处理器 Multicore Fixed and Floating-Point Digital Signal Processor
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P4P108P153P156P208
封装尺寸在P243
标记信息在P243P244
封装信息在P241P243P244
功能描述在P73
技术参数、封装参数在P116P120P121P122P123P124P125P126P127P128P129P130
应用领域在P2P228
电气规格在P97P117P118P120P121P122P123P124P125P126P127P128
型号编号列表在P116
导航目录
TMS320C6678ACYPA数据手册
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Multicore Fixed and Floating-Point Digital Signal Processor
TMS320C6678
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and
other important disclaimers. PRODUCTION DATA.
Check for Evaluation Modules (EVM): TMS320C6678
SPRS691E—November 2010—Revised March 2014
1 TMS320C6678 Features and Description
1.1 Features
• Eight TMS320C66x™ DSP Core Subsystems (C66x
CorePacs), Each with
– 1.0 GHz, 1.25 GHz, or 1.4 GHz C66x
Fixed/Floating-Point CPU Core
› 44.8 GMAC/Core for Fixed Point @ 1.4 GHz
› 22.4 GFLOP/Core for Floating Point @ 1.4 GHz
–Memory
› 32K Byte L1P Per Core
› 32K Byte L1D Per Core
› 512K Byte Local L2 Per Core
• Multicore Shared Memory Controller (MSMC)
– 4096KB MSM SRAM Memory Shared by Eight DSP
C66x CorePacs
– Memory Protection Unit for Both MSM SRAM and
DDR3_EMIF
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with Queue
Manager
– Packet-Based DMA for Zero-Overhead Transfers
• Network Coprocessor
– Packet Accelerator Enables Support for
› Transport Plane IPsec, GTP-U, SCTP, PDCP
› L2 User Plane PDCP (RoHC, Air Ciphering)
› 1-Gbps Wire-Speed Throughput at 1.5 MPackets
Per Second
– Security Accelerator Engine Enables Support for
› IPSec, SRTP, 3GPP, WiMAX Air Interface, and
SSL/TLS Security
› ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC,
GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1,
SHA-2 (256-bit Hash), MD5
› Up to 2.8 Gbps Encryption Speed
•Peripherals
– Four Lanes of SRIO 2.1
› 1.24/2.5/3.125/5 GBaud Operation Supported Per
Lane
› Supports Direct I/O, Message Passing
› Supports Four 1×, Two 2×, One 4×, and Two 1× +
One 2× Link Configurations
–PCIe Gen2
› Single Port Supporting 1 or 2 Lanes
›Supports Up To 5 GBaud Per Lane
–HyperLink
› Supports Connections to Other KeyStone
Architecture Devices Providing Resource
Scalability
› Supports up to 50 Gbaud
– Gigabit Ethernet (GbE) Switch Subsystem
›Two SGMII Ports
› Supports 10/100/1000 Mbps Operation
– 64-Bit DDR3 Interface (DDR3-1600)
› 8G Byte Addressable Memory Space
– 16-Bit EMIF
– Two Telecom Serial Ports (TSIP)
› Supports 1024 DS0s Per TSIP
› Supports 2/4/8 Lanes at 32.768/16.384/8.192 Mbps
Per Lane
–UART Interface
–I
2
C Interface
–16 GPIO Pins
–SPI Interface
– Semaphore Module
– Sixteen 64-Bit Timers
– Three On-Chip PLLs
• Commercial Temperature:
– 0°C to 85°C
• Extended Temperature:
–-40°C to 100°C
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