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TMS320C6745BPTPD4 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
LQFP-176
描述:
TMS320C6745 ， TMS320C6747固定/浮点数字信号处理器 TMS320C6745,TMS320C6747 Fixed/Floating-Point Digital Signal Processor
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P26P55P101Hot
原理图在P4P10P98P119P132P152P154P177P211
封装尺寸在P220P221
标记信息在P220P221P222
封装信息在P3P217P218P219P220P221P222
技术参数、封装参数在P60P64P65P66P67P68P69P70P71P72P73P74
应用领域在P2P227
电气规格在P63P64P65P66P67P68P69P70P71P72P73P74
导航目录
TMS320C6745BPTPD4数据手册
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TMS320C6745, TMS320C6747
SPRS377F –SEPTEMBER 2008–REVISED JUNE 2014
www.ti.com
• PRUSS can be Disabled via Software to – RMII Media-Independent Interface
Save Power
– Management Data I/O (MDIO) Module
– Standard Power-Management Mechanism
• Real-Time Clock with 32-kHz Oscillator and
Separate Power Rail (TMS320C6747 Only)
• Clock Gating
• One 64-Bit General-Purpose Timer (Configurable
• Entire Subsystem Under a Single PSC Clock
as Two 32-Bit Timers)
Gating Domain
• One 64-Bit General-Purpose Watchdog Timer
– Dedicated Interrupt Controller
(Configurable as Two 32-Bit General-Purpose
– Dedicated Switched Central Resource
Timers)
• USB 1.1 OHCI (Host) with Integrated PHY (USB1)
• Three Enhanced Pulse Width Modulators
(TMS320C6747 Only)
(eHRPWMs):
• USB 2.0 OTG Port with Integrated PHY (USB0)
– Dedicated 16-Bit Time-Base Counter with
– USB 2.0 High- and Full-Speed Client
Period and Frequency Control
(TMS320C6747)
– 6 Single Edge, 6 Dual Edge Symmetric, or 3
– USB 2.0 Full-Speed Client (TMS320C6745)
Dual Edge Asymmetric Outputs
– USB 2.0 High-, Full-, and Low-Speed Host
– Dead-Band Generation
(TMS320C6747)
– PWM Chopping by High-Frequency Carrier
– USB 2.0 Full- and Low-Speed Host
– Trip Zone Input
(TMS320C6745)
• Three 32-Bit Enhanced Capture (eCAP) Modules:
– High-Speed Functionality Available on
– Configurable as 3 Capture Inputs or 3 Auxiliary
TMS320C6747 Device Only
Pulse Width Modulator (APWM) Outputs
– End Point 0 (Control)
– Single-Shot Capture of up to Four Event Time-
– End Points 1,2,3,4 (Control, Bulk, Interrupt or
Stamps
ISOC) RX and TX
• Two 32-Bit Enhanced Quadrature Encoder Pulse
• Three Multichannel Audio Serial Ports (McASPs):
(eQEP) Modules
– TMS320C6747 Supports 3 McASPs
• TMS320C6747 Device:
– TMS320C6745 Supports 2 McASPs
– 256-Ball Pb-Free Plastic Ball Grid Array (PBGA)
– Six Clock Zones and 28 Serial Data Pins
[ZKB Suffix], 1.0-mm Ball Pitch
– Supports TDM, I2S, and Similar Formats
• TMS320C6745 Device:
– DIT-Capable (McASP2)
– 176-pin PowerPAD™ Plastic Quad Flat Pack
– FIFO Buffers for Transmit and Receive
[PTP suffix], 0.5-mm Pin Pitch
• 10/100 Mbps Ethernet MAC (EMAC):
• Commercial, Industrial, Extended, or Automotive
– IEEE 802.3 Compliant (3.3-V I/O Only)
Temperature
1.2 Applications
• A/V Receivers • Home Theatre Systems
• Automotive Amplifiers • Professional Audio
• Soundbars • Network Streaming Audio
1.3 Description
The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP
core. It consumes significantly lower power than other members of the TMS320C6000™ platform of
DSPs.
The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design
manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .
The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program
cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-
associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared
between program and data space. L2 memory can be configured as mapped memory, cache, or
combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional
128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting
DSP performance.
2 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Copyright © 2008–2014, Texas Instruments Incorporated
Processor
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