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器件3D模型￥ 110.627
TMS320DM6446ZWT 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
DSP数字信号处理器
封装:
LFBGA-361
描述:
数字媒体系统级芯片 Digital Media System-on-Chip
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P21P71Hot
原理图在P5P84P93P94
封装尺寸在P229
封装信息在P228P229
技术参数、封装参数在P14P85P88P89P90P91P92P93P94P95P96P97
应用领域在P2P231
电气规格在P14P87P88P89P90P91P92P93P94P95P96P97
导航目录
TMS320DM6446ZWT数据手册
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1 Digital Media System-on-Chip (DMSoC)
1.1 Features
TMS320DM6446
Digital Media System-on-Chip
SPRS283E – DECEMBER 2005 – REVISED MARCH 2007
• High-Performance Digital Media SoC • ARM926EJ-S Core
– 594-MHz C64x+™ Clock Rate – Support for 32-Bit and 16-Bit (Thumb®
Mode) Instruction Sets
– 297-MHz ARM926EJ-S™ Clock Rate
– DSP Instruction Extensions and Single
– Eight 32-Bit C64x+ Instructions/Cycle
Cycle MAC
– 4752 C64x+ MIPS
– ARM® Jazelle® Technology
– Fully Software-Compatible With C64x /
– EmbeddedICE-RT™ Logic for Real-Time
ARM9™
Debug
• Advanced Very-Long-Instruction-Word (VLIW)
• ARM9 Memory Architecture
TMS320C64x+™ DSP Core
– 16K-Byte Instruction Cache
– Eight Highly Independent Functional Units
– 8K-Byte Data Cache
• Six ALUs (32-/40-Bit), Each Supports
– 16K-Byte RAM
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
– 8K-Byte ROM
• Two Multipliers Support Four 16 x 16-Bit
• Embedded Trace Buffer™ (ETB11™) With 4KB
Multiplies (32-Bit Results) per Clock
Memory for ARM9 Debug
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
• Endianness: Little Endian for ARM and DSP
Results) per Clock Cycle
• Video Processing Subsystem
– Load-Store Architecture With Non-Aligned
– Front End Provides:
Support
• CCD and CMOS Imager Interface
– 64 32-Bit General-Purpose Registers
• BT.601/BT.656 Digital YCbCr 4:2:2
– Instruction Packing Reduces Code Size
(8-/16-Bit) Interface
– All Instructions Conditional
• Preview Engine for Real-Time Image
– Additional C64x+™ Enhancements
Processing
• Protected Mode Operation
• Glueless Interface to Common Video
• Exceptions Support for Error Detection
Decoders
and Program Redirection
• Histogram Module
• Hardware Support for Modulo Loop
• Auto-Exposure, Auto-White Balance and
Operation
Auto-Focus Module
• C64x+ Instruction Set Features
• Resize Engine
– Byte-Addressable (8-/16-/32-/64-Bit Data)
• Resize Images From 1/4x to 4x
– 8-Bit Overflow Protection
• Separate Horizontal/Vertical Control
– Bit-Field Extract, Set, Clear
– Back End Provides:
– Normalization, Saturation, Bit-Counting
• Hardware On-Screen Display (OSD)
– Compact 16-Bit Instructions
• Four 54-MHz DACs for a Combination of
– Additional Instructions to Support Complex
• Composite NTSC/PAL Video
Multiplies
• Luma/Chroma Separate Video
• C64x+ L1/L2 Memory Architecture
(S-video)
– 32K-Byte L1P Program RAM/Cache (Direct
• Component (YPbPr or RGB) Video
Mapped)
(Progressive)
– 80K-Byte L1D Data RAM/Cache (2-Way
• Digital Output
Set-Associative)
• 8-/16-bit YUV or up to 24-Bit RGB
– 64K-Byte L2 Unified Mapped RAM/Cache
• HD Resolution
(Flexible RAM/Cache Allocation)
• Up to 2 Video Windows
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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