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TMS320F28069PNT 产品设计参考手册 - TI（德州仪器）
制造商:
TI（德州仪器）
分类:
微控制器
封装:
LQFP-80
描述:
TEXAS INSTRUMENTS TMS320F28069PNT 微控制器, 32位, Piccolo, C2000, 90 MHz, 256 KB, 100 KB, 80 引脚, LQFP
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P9P82Hot
典型应用电路图在P46P97
原理图在P3P80P94P99P108P120P134P136P139
封装尺寸在P172P173P174P175
标记信息在P172P173P174P175P176
封装信息在P2P163P172P173P174P175P176
技术参数、封装参数在P19P20P21P22P23P24P25P26P27P28P29P30
应用领域在P2P72P133P137P156P157P158P177
电气规格在P20P86P95
型号编号列表在P120
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TMS320F28069PNT数据手册
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMS320F28069
,
TMS320F28068
,
TMS320F28067
,
TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
SPRS698F –NOVEMBER 2010–REVISED MARCH 2016
TMS320F2806x Piccolo™ Microcontrollers
1 Device Overview
1
1.1 Features
1
• High-Efficiency 32-Bit CPU (TMS320C28x)
– 90 MHz (11.11-ns Cycle Time)
– 16 × 16 and 32 × 32 Multiply and Accumulate
(MAC) Operations
– 16 × 16 Dual MAC
– Harvard Bus Architecture
– Atomic Operations
– Fast Interrupt Response and Processing
– Unified Memory Programming Model
– Code-Efficient (in C/C++ and Assembly)
• Floating-Point Unit (FPU)
– Native Single-Precision Floating-Point
Operations
• Programmable Control Law Accelerator (CLA)
– 32-Bit Floating-Point Math Accelerator
– Executes Code Independently of the Main CPU
• Viterbi, Complex Math, CRC Unit (VCU)
– Extends C28x Instruction Set to Support
Complex Multiply, Viterbi Operations, and Cyclic
Redundency Check (CRC)
• Embedded Memory
– Up to 256KB of Flash
– Up to 100KB of RAM
– 2KB of One-Time Programmable (OTP) ROM
• 6-Channel Direct Memory Access (DMA)
• Low Device and System Cost
– Single 3.3-V Supply
– No Power Sequencing Requirement
– Integrated Power-on Reset and Brown-out
Reset
– Low-Power Operating Modes
– No Analog Support Pin
• Endianness: Little Endian
• JTAG Boundary Scan Support
– IEEE Standard 1149.1-1990 Standard Test
Access Port and Boundary Scan Architecture
• Clocking
– Two Internal Zero-Pin Oscillators
– On-Chip Crystal Oscillator/External Clock Input
– Watchdog Timer Module
– Missing Clock Detection Circuitry
• Peripheral Interrupt Expansion (PIE) Block That
Supports All Peripheral Interrupts
• Three 32-Bit CPU Timers
• Advanced Control Peripherals
• Up to 8 Enhanced Pulse-Width Modulator (ePWM)
Modules
– 16 PWM Channels Total (8 HRPWM-Capable)
– Independent 16-Bit Timer in Each Module
• Three Input Enhanced Capture (eCAP) Modules
• Up to 4 High-Resolution Capture (HRCAP)
Modules
• Up to 2 Enhanced Quadrature Encoder Pulse
(eQEP) Modules
• 12-Bit Analog-to-Digital Converter (ADC), Dual
Sample-and-Hold (S/H)
– Up to 3.46 MSPS
– Up to 16 Channels
• On-Chip Temperature Sensor
• 128-Bit Security Key and Lock
– Protects Secure Memory Blocks
– Prevents Reverse-Engineering of Firmware
• Serial Port Peripherals
– Two Serial Communications Interface (SCI)
[UART] Modules
– Two Serial Peripheral Interface (SPI) Modules
– One Inter-Integrated-Circuit (I
2
C) Bus
– One Multichannel Buffered Serial Port (McBSP)
Bus
– One Enhanced Controller Area Network (eCAN)
– Universal Serial Bus (USB) 2.0
(see Device Comparison Table for Availability)
• Full-Speed Device Mode
• Full-Speed or Low-Speed Host Mode
• Up to 54 Individually Programmable, Multiplexed
General-Purpose Input/Output (GPIO) Pins With
Input Filtering
• Advanced Emulation Features
– Analysis and Breakpoint Functions
– Real-Time Debug Through Hardware
• 2806x Packages
– 80-Pin PFP and 100-Pin PZP PowerPAD™
Thermally Enhanced Thin Quad Flatpacks
(HTQFPs)
– 80-Pin PN and 100-Pin PZ Low-Profile Quad
Flatpacks (LQFPs)
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