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AD8331-EVALZ 用户编程技术手册 - ADI（亚德诺）
制造商:
ADI（亚德诺）
分类:
开发套件
描述:
ANALOG DEVICES AD8331-EVALZ. 评估板, 可变增益放大器
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P8P9P10P54Hot
原理图在P1P24P25P27P28P35P36P37P40P44P49
封装尺寸在P53
型号编码规则在P55
功能描述在P1P8P9P10P39P43P47P54
技术参数、封装参数在P1P4P7
应用领域在P1P26P27P28P29P30P32
电气规格在P12
导航目录
AD8331-EVALZ数据手册
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若手册格式错乱，请下载阅览PDF原文件
AD8331/AD8332/AD8334 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
1
ENABLE INTERFACE
(PIN ENB, PIN ENBL, PIN ENBV)
Logic Level to Enable Power 2.25 5 V
Logic Level to Disable Power 0 1.0 V
Input Resistance Pin ENB 25 kΩ
Pin ENBL 40 kΩ
Pin ENBV 70 kΩ
Power-Up Response Time V
INH
= 30 mV p-p 300 µs
V
INH
= 150 mV p-p 4 ms
HILO GAIN RANGE INTERFACE (PIN HILO)
Logic Level to Select HI Gain Range 2.25 5 V
Logic Level to Select LO Gain Range 0 1.0 V
Input Resistance 50 kΩ
OUTPUT CLAMP INTERFACE (PIN RCLMP; HI OR
LO GAIN)
Accuracy
HILO = LO R
CLMP
= 2.74 kΩ, V
OUT
= 1 V p-p (clamped) ±50 mV
HILO = HI R
CLMP
= 2.21 kΩ, V
OUT
= 1 V p-p (clamped) ±75 mV
MODE INTERFACE (PIN MODE)
Logic Level for Positive Gain Slope 0 1.0 V
Logic Level for Negative Gain Slope 2.25 5 V
Input Resistance 200 kΩ
POWER SUPPLY (PIN VPS1, PIN VPS2,
PIN VPSV, PIN VPSL, PIN VPOS)
Supply Voltage 4.5 5.0 5.5 V
Quiescent Current per Channel
AD8331 20 25 mA
AD8332 22 27.5 32 mA
AD8334 24 29.5 34
Power Dissipation per Channel No signal
AD8331 125 mW
AD8332, AD8334 138 mW
Power-Down Current
VGA and LNA disabled
AD8331 50 240 400 µA
AD8332 50 300 600 µA
AD8334 50 600 1200 µA
LNA Current
AD8331 (ENBL) Each channel 7.5 11 15 mA
AD8332, AD8334 (ENBL)
Each channel
7.5
12
15
mA
VGA Current
AD8331 (ENBV) 7.5 14 20 mA
AD8332, AD8334 (ENBV) 7.5 17 20 mA
PSRR V
GAIN
= 0 V, f = 100 kHz −68 dB
1
All dBm values are referred to 50 Ω.
2
The absolute gain refers to the theoretical gain expression in Equation 1.
3
Best-fit to linear-in-dB curve.
4
The current is limited to ±1 mA typical.
Rev. H | Page 6 of 56
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