Datasheet 搜索 > 微控制器 > ATMEL(爱特美尔) > ATMEGA128A-MU 数据手册 > ATMEGA128A-MU 用户编程技术手册 6/475 页


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ATMEGA128A-MU 用户编程技术手册 - ATMEL(爱特美尔)
制造商:
ATMEL(爱特美尔)
分类:
微控制器
封装:
QFN-64
描述:
ATMEL ATMEGA128A-MU 微控制器, 8位, 低功率高性能, ATmega, 16 MHz, 128 KB, 4 KB, 64 引脚, QFN
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P14P37P96P139P140P194P217P237P240P248P308Hot
原理图在P12P22P94P140P145P146P148P150P194P196P197P198
封装尺寸在P469P470
型号编码规则在P11P474
封装信息在P11P469
技术参数、封装参数在P414
应用领域在P42P69P80P85P365P369P382P383P475
电气规格在P87P94P95P414P474
导航目录
ATMEGA128A-MU数据手册
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25.2. Overview...................................................................................................................................247
25.3. Clock Generation......................................................................................................................249
25.4. Frame Formats.........................................................................................................................252
25.5. USART Initialization..................................................................................................................253
25.6. Data Transmission – The USART Transmitter......................................................................... 254
25.7. Data Reception – The USART Receiver.................................................................................. 257
25.8. Asynchronous Data Reception.................................................................................................260
25.9. Multi-Processor Communication Mode.....................................................................................263
25.10. Examples of Baud Rate Setting............................................................................................... 264
25.11. Register Description................................................................................................................. 267
26. TWI - Two-wire Serial Interface............................................................................. 276
26.1. Features................................................................................................................................... 276
26.2. Overview...................................................................................................................................276
26.3. Two-Wire Serial Interface Bus Definition..................................................................................278
26.4. Data Transfer and Frame Format.............................................................................................279
26.5. Multi-master Bus Systems, Arbitration and Synchronization....................................................282
26.6. Using the TWI...........................................................................................................................283
26.7. Multi-master Systems and Arbitration.......................................................................................300
26.8. Register Description................................................................................................................. 301
27. Analog Comparator............................................................................................... 308
27.1. Overview...................................................................................................................................308
27.2. Analog Comparator Multiplexed Input...................................................................................... 308
27.3. Register Description................................................................................................................. 309
28. ADC - Analog to Digital Converter.........................................................................313
28.1. Features................................................................................................................................... 313
28.2. Overview...................................................................................................................................313
28.3. Starting a Conversion...............................................................................................................315
28.4. Prescaling and Conversion Timing...........................................................................................315
28.5. Changing Channel or Reference Selection.............................................................................. 317
28.6. ADC Noise Canceler................................................................................................................ 319
28.7. ADC Conversion Result............................................................................................................322
28.8. Register Description................................................................................................................. 324
29. JTAG Interface and On-chip Debug System..........................................................334
29.1. Features................................................................................................................................... 334
29.2. Overview...................................................................................................................................334
29.3. TAP – Test Access Port............................................................................................................335
29.4. TAP Controller.......................................................................................................................... 336
29.5. Using the Boundary-scan Chain...............................................................................................337
29.6. Using the On-chip Debug System............................................................................................ 337
29.7. On-chip Debug Specific JTAG Instructions.............................................................................. 338
29.8. Using the JTAG Programming Capabilities.............................................................................. 339
29.9. Bibliography..............................................................................................................................339
29.10. IEEE 1149.1 (JTAG) Boundary-scan........................................................................................339
29.11. Data Registers..........................................................................................................................340
29.12. Boundry-scan Specific JTAG Instructions................................................................................ 342
Atmel ATmega128A [DATASHEET]
Atmel-8151J-8-bit AVR Microcontroller_Datasheet_Complete-09/2015
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