Datasheet 搜索 > 8位微控制器 > Microchip（微芯） > ATMEGA128RFA1-ZU 数据手册 > ATMEGA128RFA1-ZU 用户编程技术手册 2/570 页
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ATMEGA128RFA1-ZU 用户编程技术手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
8位微控制器
封装:
QFN-64
描述:
ATmega 系列 16 MHz 128 KB 闪存 4 KB SRAM 8 位 微控制器 - QFN-64
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P2P5P192P229P247P312P560Hot
典型应用电路图在P82P155P500
原理图在P3P9P31P43P76P78P81P83P91P168P190P229
型号编码规则在P552
封装信息在P553
功能描述在P63P334
技术参数、封装参数在P77P90P102P512P523P525
应用领域在P1P92P157P180P216P220P455P470P471P500P502P514
电气规格在P73P156P166P178P179P190P207P208P416P418P512P516
导航目录
ATMEGA128RFA1-ZU数据手册
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2
8266F-MCU Wireless-09/14
ATmega128RFA1
1 Pin Configurations
Figure 1-1. Pinout ATmega128RFA1
Note:
The large center pad underneath the QFN/MLF package is made of metal and internally connected
to AVSS. It should be soldered or glued to the board to ensure good mechanical stability. If the
center pad is left unco
nnected, the package might loosen from the board. It is not recommended to
use the exposed paddle as a replacement of the regular AVSS pins.
2 Disclaimer
Typical values contained in this datasheet are based on simulation and characterization
results of other AVR microcontrollers and radio transceivers manufactured in a similar
process technology. Minimum and Maximum values will be available after the device is
characterized.
1
[PF3:ADC3:DIG4]
[PF2:ADC2:DIG2]
2
3
[PF5:ADC5:TMS]
[PF4:ADC4:TCK]
4
5
[PF7:ADC7:TDI]
[PF6:ADC6:TDO]
6
7
[RFP]
[AVSS_RFP]
8
9
[AVSS_RFN]
[RFN]
10
11
[RSTN]
[TST]
12
13
14
[RSTON]
[PG0:DIG3]
56
55
54
53
52
51
62
61
60
59
58
57
64
63
ATmega128RFA1
Exposed paddle: [AVSS]
[DVSS]
[PE0:RXD0:PCINT8]
[PE1:TXD0]
[PE2:XCK0:AIN0]
[CLKI]
[DEVDD]
[DVSS]
[PB0:SSN:PCINT0]
[PB1:SCK:PCINT1]
[PB2:MOSI:PDI:PCINT2]
[PB3:MISO:PDO:PCINT3]
[PB4:OC2A:PCINT4]
[PB5:OC1A:PCINT5]
[PB6:OC1B:PCINT6]
31
32
17
18
19
20
21
23
22
24
25
26
27
0
28
[PD3:TXD1:INT3]
[PD2:RXD1:INT2]
[PD1:SDA:INT1]
[PD0:SCL:INT0]
[DVSS]
[DEVDD]
[DVDD]
[DVDD]
[DVSS:DSVSS]
[PG5:OC0B]
[PG4:TOSC1]
[PG3:TOSC2]
[PD7:T0]
[PD6:T1]
42
41
40
39
38
37
36
35
34
33
48
47
46
45
15
16
[PG1:DIG1]
[PG2:AMR]
[PB7:OC0A:OC1C:PCINT7]
[DEVDD]
44
43
29
0
30
[PD5:XCK1]
[PD4:ICP1]
50
49
Index corner
[DEVDD]
[PE7:ICP3:INT7:CLKO]
[PE6:T3:INT6]
[PE5:O
C3C:INT5]
[PE4:OC3B:INT4]
[PE3:OC3A:AIN1]
[XTAL2]
[DVSS]
[PF1:ADC1]
[PF0:ADC0]
[AREF]
[AVSS]
[AVDD]
[EVDD]
[AVSS:ASVSS]
[XTAL1]
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