Datasheet 搜索 > 微控制器 > ATMEL（爱特美尔） > ATMEGA162V-8MI 数据手册 > ATMEGA162V-8MI 用户编程技术手册 6/22 页
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ATMEGA162V-8MI 用户编程技术手册 - ATMEL（爱特美尔）
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ATMEL（爱特美尔）
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微控制器
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VFQFN-44
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ATMEGA162V-8MI数据手册
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6
2513KS–AVR–07/09
ATmega162/V
Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega162 as listed on page
78.
Port E(PE2..PE0) Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega162 as listed on page
81.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
Reset, even if the clock is not running. The minimum pulse length is given in Table 18 on page
48. Shorter pulses are not guaranteed to generate a reset.
XTAL1 Input to the Inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the Inverting Oscillator amplifier.
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