Datasheet 搜索 > 微控制器 > Microchip（微芯） > ATMEGA256RFR2-ZU 数据手册 > ATMEGA256RFR2-ZU 用户编程技术手册 6/611 页
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ATMEGA256RFR2-ZU 用户编程技术手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
QFN-64
描述:
8 位 megaAVR 微控制器，32KB 到 256KB 闪存我们在 RS Components 提供多款来自 Atmel 的 megaAVR 8 位微控制器。 每个微控制器均基于增强型 RISC 体系结构，并具有 QTouch 库支持。 所有微控制器类型具有不同 Kb 的系统内可编程内存、EEPROM 和 SRAM 以及不同引脚和封装类型。 **megaAVR 8 位微控制器类型** ATmega32 ATmega64 ATmega128 ATmega324 ATmega325 ATmega406 ATmega640 ATmega644 ATmega645 ATmega1280 ATmega1281 ATmega1284 ATmega2560 ATmega2561 ATmega3250 ATmega6450
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P2P5P221P258P276P341Hot
典型应用电路图在P87P181P540
原理图在P3P9P33P46P80P82P85P87P96P194P219P258
型号编码规则在P594P595P596
封装信息在P597
功能描述在P67P363
技术参数、封装参数在P81P95P105P110P553P564P566
应用领域在P1P97P183P209P245P249P487P504P505P540P542P555
电气规格在P77P182P192P206P207P219P236P237P446P448P553P557
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ATMEGA256RFR2-ZU数据手册
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6
8393C-MCU Wireless-09/14
ATmega256/128/64RFR2
current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port E also provides functions of various special features of the
ATmega256/128/64RFR2.
3.2.10 Port F (PF7...PF0)
Port F is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port F output buffers have symmetrical drive characteristics with both high sink
and source capability. As inputs, Port F pins that are externally pulled low will source
current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
Port F also provides functions of various special features of the
ATmega256/128/64RFR2.
3.2.11 Port G (PG5…PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port G output buffers have symmetrical drive characteristics with both high
sink and source capability. However the driver strength of PG3 and PG4 is reduced
compared to the other port pins. The output voltage drop (V
OH
, V
OL
) is higher while the
leakage current is smaller. As inputs, Port G pins that are externally pulled low will
source current if the pull-up resistors are activated. The Port G pins are tri-stated when
a reset condition becomes active, even if the clock is not running.
Port G also provides functions of various special features of the
ATmega256/128/64RFR2.
3.2.12 AVSS_RFP
AVSS_RFP is a dedicated ground pin for the bi-directional, differential RF I/O port.
3.2.13 AVSS_RFN
AVSS_RFN is a dedicated ground pin for the bi-directional, differential RF I/O port.
3.2.14 RFP
RFP is the positive terminal for the bi-directional, differential RF I/O port.
3.2.15 RFN
RFN is the negative terminal for the bi-directional, differential RF I/O port.
3.2.16 RSTN
Reset input. A low level on this pin for longer than the minimum pulse length will
generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to
generate a reset.
3.2.17 RSTON
Reset output. A low level on this pin indicates a reset initiated by the internal reset
sources or the pin RSTN.
3.2.18 XTAL1
Input to the inverting 16MHz crystal oscillator amplifier. In general a crystal between
XTAL1 and XTAL2 provides the 16MHz reference clock of the radio transceiver.
3.2.19 XTAL2
Output of the inverting 16MHz crystal oscillator amplifier.
3.2.20 AREF
Reference voltage output of the A/D Converter. In general this pin is left open.
3.2.21 TST
Programming and test mode enable pin. If pin TST is not used pull it to low.
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