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ATMEGA328P-MU 用户编程技术手册 - Microchip(微芯)
制造商:
Microchip(微芯)
分类:
微控制器
封装:
QFN-32
描述:
ATmega 系列 20 MHz 32 KB 闪存 2 KB SRAM 8 位 微控制器 - QFN-32
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P3P4Hot
原理图在P6
封装尺寸在P24P25P26P27P28P48
型号编码规则在P16P17P18P19P20P21P22P23P48
封装信息在P24P48P49
应用领域在P50
电气规格在P48
导航目录
ATMEGA328P-MU数据手册
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6
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271JS-AVR- ATmega-Datasheet_11/2015
2. Overview
The ATmega48A/PA/88A/PA/168A/PA/328/P is a low-power CMOS 8-bit microcontroller based on the AVR
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing the
system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are
directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one
single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
PORT C (7)PORT B (8)PORT D (8)
USART 0
8bit T/C 2
16bit T/C 18bit T/C 0 A/D Conv.
Internal
Bandgap
Analog
Comp.
SPI TWI
SRAMFlash
EEPROM
Watchdog
Oscillator
Watchdog
Timer
Oscillator
Circuits /
Clock
Generation
Power
Supervision
POR / BOD &
RESET
VCC
GND
PROGRAM
LOGIC
debugWIRE
2
GND
AREF
AVCC
DATA BUS
ADC[6..7]PC[0..6]PB[0..7]PD[0..7]
6
RESET
XTAL[1..2]
CPU
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