Datasheet 搜索 > 微控制器 > ATMEL（爱特美尔） > ATMEGA32U2-AU 数据手册 > ATMEGA32U2-AU 用户编程技术手册 6/24 页
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ATMEGA32U2-AU 用户编程技术手册 - ATMEL（爱特美尔）
制造商:
ATMEL（爱特美尔）
分类:
微控制器
封装:
TQFP-32
描述:
ATMEL ATMEGA32U2-AU 芯片, 8位微控制器, AVR, 32K闪存, USB, 32TQFP
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ATMEGA32U2-AU数据手册
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6
7766GS–AVR–02/2014
ATmega16/32U4
Only bits 6 and 7 are present on the product pinout.
Port C also serves the functions of special features of the ATmega16U4/ATmega32U4 as listed
on page 75.
2.2.5 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega16U4/ATmega32U4
as listed on page 77.
2.2.6 Port E (PE6,PE2)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Only bits 2 and 6 are present on the product pinout.
Port E also serves the functions of various special features of the ATmega16U4/ATmega32U4
as listed on page 80.
2.2.7 Port F (PF7..PF4, PF1,PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter channels are not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers
have symmetrical drive characteristics with both high sink and source capability. As inputs, Port
F pins that are externally pulled low will source current if the pull-up resistors are activated. The
Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running.
Bits 2 and 3 are not present on the product pinout.
Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull-
up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.
2.2.8 D-
USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB D-
connector pin with a serial 22 Ohms resistor.
2.2.9 D+
USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+
connector pin with a serial 22 Ohms resistor.
2.2.10 UGND
USB Pads Ground.
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