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3
8246B–AVR–09/11
ATtiny2313A/4313
1.1 Pin Descriptions
1.1.1 VCC
Digital supply voltage.
1.1.2 GND
Ground.
1.1.3 Port A (PA2..PA0)
Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability, except PA2 which has the RESET
capability. To use pin PA2 as I/O pin, instead of
RESET pin, program (“0”) RSTDISBL fuse. As inputs, Port A pins that are externally pulled low
will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port A also serves the functions of various special features of the ATtiny2313A/4313 as listed on
page 62.
1.1.4 Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny2313A/4313 as listed on
page 63.
1.1.5 Port D (PD6..PD0)
Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATtiny2313A/4313 as listed on
page 67.
1.1.6 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided that the reset pin has not been disabled. The
minimum pulse length is given in Table 22-3 on page 201. Shorter pulses are not guaranteed to
generate a reset. The Reset Input is an alternate function for PA2 and dW.
The reset pin can also be used as a (weak) I/O pin.
1.1.7 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL1
is an alternate function for PA0.

ATTINY4313-SU 数据手册

ATMEL(爱特美尔)
22 页 / 0.54 MByte
ATMEL(爱特美尔)
68 页 / 9.77 MByte
ATMEL(爱特美尔)
274 页 / 5.84 MByte
ATMEL(爱特美尔)
4 页 / 0.06 MByte

ATTINY4313 数据手册

ATMEL(爱特美尔)
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AVR 20MHz 闪存:2K@x16bit
Microchip(微芯)
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Microchip(微芯)
8位 MCU微控制单元, AVR Family ATtiny4313 Series Microcontrollers, 20 MHz, 4 KB, 256 Byte, 20 引脚, QFN-EP
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