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CY7C63723C-PXC 用户编程技术手册 - Cypress Semiconductor（赛普拉斯）
制造商:
Cypress Semiconductor（赛普拉斯）
分类:
微控制器
封装:
PDIP-18
描述:
CY7C63 系列 256 B RAM 8 kB EPROM enCoRe™ USB和PS/2 控制器 - PDIP-18
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
原理图在P1P3P4
型号编码规则在P29
封装信息在P23P25P26P29
焊接温度在P24
功能描述在P20P29
技术参数、封装参数在P13P14P15P16P17P18P19P20P21P22P26
电气规格在P13P15P18
导航目录
CY7C63723C-PXC数据手册
Page:
of 37 Go
若手册格式错乱，请下载阅览PDF原文件
CY8C21334, CY8C21534
Automotive PSoC
®
Programmable System-on-Chip
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 •408-943-2600
Document Number: 001-12550 Rev. *G Revised November 23, 2010
Features
■ Automotive Electronics Council (AEC) Q100 qualified
■ Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ Low power at high speed
❐ 3.0 V to 5.25 V operating voltage
❐ Automotive temperature range: –40 C to +85 C
■ Advanced peripherals (PSoC
®
blocks)
❐ Four analog Type E PSoC blocks provide:
• Two comparators with digital-to-analog converter (DAC)
references
• Up to 10-bit single or dual, 24 channel analog-to-digital
converters (ADC)
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo-random
sequence (PRS) modules
• Full- or half-duplex UART
• SPI master or slave
• Connectable to all general purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
• Capacitive sensing application capability
■ Flexible on-chip memory
❐ 8 KB flash program storage
❐ 512 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Precision, programmable clocking
❐ Internal ±5% 24 MHz oscillator
❐ Internal low-speed, low-power oscillator for Watchdog and
Sleep functionality
❐ Optional external oscillator, up to 24 MHz
■ Programmable pin configurations
❐ 25 mA sink, 10 mA drive on all GPIO
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIO
❐ Analog input on all GPIO
❐ Configurable interrupt on all GPIO
■ Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
■ Additional system resources
❐ Inter-Integrated Circuit (I
2
C™) master, slave, or multi-master
operation up to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
Logic Block Diagram
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