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EPM7064SLC44-10 用户编程技术手册 - Intel（英特尔）
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Intel（英特尔）
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PLCC-44
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EPM7064SLC44-10数据手册
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2 Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
...and More
Features
■ Open-drain output option in MAX 7000S devices
■ Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
■ Programmable power-saving mode for a reduction of over 50% in
each macrocell
■ Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
■ 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic
pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat
pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
■ Programmable security bit for protection of proprietary designs
■ 3.3-V or 5.0-V operation
–MultiVolt
TM
I/O interface operation, allowing devices to
interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is
not available in 44-pin packages)
– Pin compatible with low-voltage MAX 7000A and MAX 7000B
devices
■ Enhanced features available in MAX 7000E and MAX 7000S devices
– Six pin- or logic-driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Fast input setup times provided by a dedicated path from I/O
pin to macrocell registers
– Programmable output slew-rate control
■ Software design support and automatic place-and-route provided by
Altera’s development system for Windows-based PCs and Sun
SPARCstation, and HP 9000 Series 700/800 workstations
Table 2. MAX 7000S Device Features
Feature EPM7032S EPM7064S EPM7128S EPM7160S EPM7192S EPM7256S
Usable gates 600 1,250 2,500 3,200 3,750 5,000
Macrocells 32 64 128 160 192 256
Logic array
blocks
248101216
Maximum
user I/O pins
36 68 100 104 124 164
t
PD
(ns) 5 5 6 6 7.5 7.5
t
SU
(ns) 2.9 2.9 3.4 3.4 4.1 3.9
t
FSU
(ns) 2.5 2.5 2.5 2.5 3 3
t
CO1
(ns) 3.2 3.2 4 3.9 4.7 4.7
f
CNT
(MHz) 175.4 175.4 147.1 149.3 125.0 128.2
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