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MC68331CAG20
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MC68331CAG20数据手册
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Engineering Bulletin
General Information
EB263
MOTOROLA 5
2. Compare the base address register values for any overlap. This
procedure involves not only comparing the actual base address
registers, but also looking at the block sizes and thus the number
of address lines compared. The processor does not look at all 24
address lines when it compares for a match. Thus, two chip
selects could be interpreted as responding to the same base
address, even though their base address registers are
programmed differently.
For example, use
Table 4
. Look at the addresses to see any
overlap. The answer is yes.
Chip selects 0 and 10 conflict. Both will respond to the address $40000.
CS0 is programmed to start at $50000; however, it is programmed
incorrectly. It does not lie on an even boundary of 128 Kbytes.
(Remember that 1 K = 1024.) As shown in
Table 5
, only address lines
23 through 17 are compared for a block size of 128 Kbytes.
This is how the address decoding process works:
CSBAR0: $0504 = base address of $50000 and block size of 128 K.
23 20 19 16 15 12 11 8 7 4 3 0
$5000 = %0000 0101 0000 0000 0000 0000
For a 128-K block size, address lines 16–0 are decoded as 0. As a result,
bits 19–16 are read as a 4 instead of a 5, and CS0 responds to the
address space starting at location $40000.
However, CS10 is also programmed to respond to the address space
starting at location $40000. It is acceptable for two chip selects to
respond to the same address space; however, in this case, the option
registers are programmed for a different number of wait states. As a
result, the termination signal will be indeterminate.
To correct the problem, CSBAR0 and/or CSBAR10 must be changed. If
CSBAR0 is changed to $0404 and CSBAR10 is changed to a different,
non-overlapping base address, then $40000 is an acceptable base
address for CS0, since it is an exact multiple of 128 Kbytes.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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