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MC68340AB16E 用户编程技术手册 - NXP（恩智浦）
制造商:
NXP（恩智浦）
分类:
微处理器
封装:
QFP-144
描述:
NXP MC68340AB16E 微处理器(MPU), 32位, M68340, 16MHz, 144QFP
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MC68340AB16E数据手册
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3 AN1264 Application Note MOTOROLA
Figure 2. Memory Write Cycle Example
Figure 3. Memory Read Cycle Example
One key attribute of the JTAG Flash programmer is its flexibility. For example the jtagscan.txt input file gives
the user complete freedom in the definition of signal states during read and write bus cycles to tailor towards
specific system hardware requirements. In the memory write cycle of Figure 2, R/W is maintained low during
the chip select negation, ensuring the data direction integrity is maintained until the memory write concludes.
Also, if the memory interface does not use AS
and xDS as part of the hardware decode for memory accesses,
they need not be asserted during reads/writes. So the conclusion is that the flexibility means the bus cycles
produced can deviate from the normal operation of the processor bus cycles. Accordingly, care must be taken
not to damage the hardware. During reads for example, the data bus must be tri-stated to allow the memory
to drive the bus and avoid contention.
The JTAG programmer was also designed for simplicity. Having set up the two JTAG scan input files
(jtagscan.txt and jtaginst.txt) once for a particular processor system, simply re-compile the desired target code
to form a new s-record file and use the programmer to download the new release of software into the target
Flash EPROM. It is well suited to system software upgrades in the field.
Address(23:0)
R/W
ADDRESS OUT
xDS
AS
CS0
Data(15:8)
DATA TO MEMORY
Scan Register contents latched onto processor pins for
Bus Cycle Assertion & Termination
DATA FROM MEMORY
Address(23:0)
R/W
ADDRESS OUT
xDS
AS
CS0
Data(15:8)
ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2006
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