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PIC18F4331-E/PT 用户编程技术手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
TQFP-44
描述:
28 /40/ 44引脚增强型闪存微控制器采用纳瓦技术，高性能PWM和A / D 28/40/44-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
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PIC18F4331-E/PT数据手册
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若手册格式错乱，请下载阅览PDF原文件
2010 Microchip Technology Inc. DS30500B-page 5
PIC18F2331/2431/4331/4431
2.3 Memory Map
The code memory space extends from 0000h to 3FFFh
(16 Kbytes) in four 4-Kbyte blocks. Addresses 0000h
through 01FFh, however, define a “Boot Block” region
that is treated separately from Block 0. All of these
blocks define code protection boundaries within the
code memory space.
In contrast, code memory panels are defined in 8-Kbyte
boundaries. Panels are discussed in greater detail in
Section 3.2.
TABLE 2-2: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-4: MEMORY MAP AND THE CODE MEMORY SPACE FOR PIC18FXX31 DEVICES
Device Code Memory Size (Bytes)
PIC18F2331
000000h - 001FFFh (8K)
PIC18F4331
PIC18F2431
000000h - 003FFFh (16K)
PIC18F4431
000000h
1FFFFFh
3FFFFFh
003FFFh
Note: Sizes of memory areas not to scale.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE/DEVICE
8Kbytes
(PIC18FX331)
Address
Range
16 Kbytes
(PIC18FX431)
Address
Range
Block Code
Protection
Controlled By:
Boot Block
0000h
0FFFh
Boot Block
0000h
01FFh
CPB, WRTB, EBTRB
Block 0
0200h
0FFFh
Block 0
0200h
0FFFh
CP0, WRT0, EBTR0
Block 1
1000h
1FFFh
Block 1
1000h
1FFFh
CP1, WRT1, EBTR1
Unimplemented
Read as ‘0’
Block 2
2000h
2FFFh
CP2, WRT2, EBTR2
3FFFh
Block 3
3000h
3FFFh
CP3, WRT3, EBTR3
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