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PIC18F4553-I/P 用户编程技术手册 - Microchip(微芯)
制造商:
Microchip(微芯)
分类:
微控制器
封装:
PDIP-40
描述:
MICROCHIP PIC18F4553-I/P 微控制器, 8位, 闪存, PIC18F4xxx, 48 MHz, 32 KB, 2 KB, 40 引脚, DIP
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引脚图
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PIC18F4553-I/P数据手册
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© 2007 Microchip Technology Inc. DS39622K-page 5
PIC18F2XXX/4XXX FAMILY
For PIC18F2685/4685 devices, the code memory
space extends from 0000h to 017FFFh (96 Kbytes) in
five 16-Kbyte blocks. For PIC18F2682/4682 devices,
the code memory space extends from 0000h to
0013FFFh (80 Kbytes) in four 16-Kbyte blocks.
Addresses 0000h through 0FFFh, however, define a
“Boot Block” region that is treated separately from
Block 0. All of these blocks define code protection
boundaries within the code memory space.
The size of the Boot Block in PIC18F2685/4685 and
PIC18F2682/4682 devices can be configured as 1, 2 or
4K words (see Figure 2-4). This is done through the
BBSIZ1:BBSIZ2 bits in the Configuration register,
CONFIG4L. It is important to note that increasing the
size of the Boot Block decreases the size of Block 0.
TABLE 2-3: IMPLEMENTATION OF CODE
MEMORY
FIGURE 2-4: MEMORY MAP AND THE CODE MEMORY SPACE
FOR PIC18F2685/4685 AND PIC18F2682/4682 DEVICES
Device Code Memory Size (Bytes)
PIC18F2682
000000h-013FFFh (80K)
PIC18F4682
PIC18F2685
000000h-017FFFh (96K)
PIC18F4685
000000h
200000h
3FFFFFh
01FFFFh
Note: Sizes of memory areas are not to scale.
* Boot Block size is determined by the BBSIZ1:BBSIZ2 bits in the CONFIG4L register.
Code Memory
Unimplemented
Read as ‘0’
Configuration
and ID
Space
MEMORY SIZE/DEVICE
Address
Range
96 Kbytes
(PIC18F2685/4685)
BBSIZ1:BBSIZ2
11/10 01 00
Boot
Boot
000000h
0007FFh
Block 0
000800h
000FFFh
Block 0
001000h
001FFFh
Block 0
002000h
003FFFh
Block 1
004000h
017FFFh
Unimplemented
Reads all ‘0’s
01FFFFh
Block*
Block*
11/10 01 00
80 Kbytes
(PIC18F2682/4682)
Boot
Block*
Boot
Block*
Boot
Block*
Boot
Block*
Block 0
Block 0
Block 0
Unimplemented
Reads all ‘0’s
Block 2
Block 3
Block 2
Block 1
007FFFh
008000h
013FFFh
014000h
Block 4
Block 3
Block 5
Block 4
00FFFFh
010000h
00BFFFh
00C000h
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