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PIC18F8410-I/PT
器件3D模型
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PIC18F8410-I/PT数据手册
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PIC18F8410/8490/8493 FAMILY
DS39624C-page 6 © 2007 Microchip Technology Inc.
2.3 Memory Map
The code memory space extends from 000000h to
001FFFh (8 Kbytes) in a single block for
PIC18FX310/X390/X393 devices and from 000000h to
003FFFh (16 Kbytes) in a single block for
PIC18FX410/X490/X493 devices.
TABLE 2-2 IMPLEMENTATION OF CODE
MEMORY
In addition to the code memory space, there are three
blocks in the configuration and ID space that are
accessible to the user through table reads and table
writes (in ICSP mode). Their locations in the memory
map are shown in Figure 2-5.
Users may store identification information (user ID) in
eight ID registers. These ID registers are mapped in
addresses 200000h through 200007h. The ID locations
read out normally, even after code protection is applied.
Locations 300000h through 30000Dh are reserved for
the configuration bits. These bits select various device
options and are described in Section 5.0
“Configuration Word”. These configuration bits read
out normally, even after code protection.
Locations 3FFFFEh and 3FFFFFh are reserved for the
device ID bits. These bits are read-only bits. These bits
may be used by the programmer to identify what device
type is being programmed and are described in
Section 5.0 “Configuration Word”. These device ID
bits read out normally, even after code protection.
2.3.1 MEMORY ADDRESS POINTER
Memory in the address space 0000000h to 3FFFFFh is
addressed via the Table Pointer, which is comprised of
three pointer registers:
TBLPTRU, at RAM address 0FF8h
TBLPTRH, at RAM address 0FF7h
TBLPTRL, at RAM address 0FF6h
The 4-bit command, 0000’ (core instruction), is used to
load the Table Pointer prior to using many read or write
operations.
Device Code Memory Size (Bytes)
PIC18F6310
000000h-001FFFh (8K)
PIC18F8310
PIC18F6390
PIC18F6393
PIC18F8390
PIC18F8393
PIC18F6410
000000h-003FFFh (16K)
PIC18F8410
PIC18F6490
PIC18F6493
PIC18F8490
PIC18F8493
TBLPTRU TBLPTRH TBLPTRL
Addr[21:16] Addr[15:8] Addr[7:0]

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