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PIC24FJ128GB202-I/SP 用户编程技术手册 - Microchip（微芯）
制造商:
Microchip（微芯）
分类:
微控制器
封装:
DIP-28
描述:
MICROCHIP PIC24FJ128GB202-I/SP 微控制器, 16位, 通用, PIC24FJ, 32 MHz, 128 KB, 8 KB, 28 引脚, SDIP
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PIC24FJ128GB202-I/SP数据手册
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2012-2015 Microchip Technology Inc. DS30000510F-page 1
PIC24FJXXXGA2/GB2 FAMILIES
1.0 DEVICE OVERVIEW
This document defines the programming specification
for the PIC24FJXXXGA2/GB2 families of microcontroller
devices. This programming specification is required only
for those developing programming support for the
PIC24FJXXXGA2/GB2 devices. Customers using only
one of these devices should use development tools that
already provide support for device programming.
This programming specification is specific to the
following devices:
2.0 PROGRAMMING OVERVIEW
OF PIC24FJXXXGA2/GB2
DEVICES
There are two methods of programming the
PIC24FJXXXGA2/GB2 devices discussed in this
programming specification. They are:
• In-Circuit Serial Programming™ (ICSP™)
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
The ICSP programming method is the most direct
method to program the device; however, it is also the
slower of the two methods. It provides native, low-level
programming capability to erase, program and verify
the chip.
The Enhanced In-Circuit Serial Programming (Enhanced
ICSP) protocol uses a faster method that takes
advantage of the Programming Executive (PE), as
illustrated in Figure 2-1. The Programming Executive
provides all the necessary functionality to erase, program
and verify the chip through a small command set. The
command set allows the programmer to program the
PIC24FJXXXGA2/GB2 MCUs without having to deal
with the low-level programming protocols of the chip.
This specification is divided into major sections that
describe the programming methods independently.
Section 3.0 “Device Programming – ICSP” describes
the In-Circuit Serial Programming method. Section 4.0
“Device Programming – Enhanced ICSP” describes
the Enhanced In-Circuit Serial Programming method.
• PIC24FJ128GA204 • PIC24FJ64GA204
• PIC24FJ128GA202 • PIC24FJ64GA202
• PIC24FJ128GB204 • PIC24FJ64GB204
• PIC24FJ128GB202 • PIC24FJ64GB202
Note: The address of the Special Function
Register, TBLPAG, has moved from 32h to
54h in the devices covered in this
specification.
In those cases where legacy program-
ming specification code from other device
families is used as a basis to implement
the programming specification for the
PIC24FJXXXGA2/GB2 devices, special
care must be taken to ensure all refer-
ences to TBLPAG and NVMCON, in any
existing code, are updated with the correct
opcode hex data for the mnemonic and
operands.
PIC24FJXXXGA2/GB2 Devices:
Previous PIC24F Families:
Command
(Binary)
Data
(Hex)
Description
0000 8802A0 MOV W0, TBLPAG
Command
(Binary)
Data
(Hex)
Description
0000 880190 MOV W0, TBLPAG
PIC24FJXXXGA2/GB2 Families Flash
Programming Specification
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