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STM8AF6266TDY
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Product evolution Errata sheet
6/21 DocID18392 Rev 4
1 Product evolution
Table 3 gives a summary of the fix status.
Legend for Table 3: A = workaround available; N = no workaround available; P = partial
workaround available, ‘-’ and grayed = fixed.
Table 3. Product evolution summary
Section Limitation Rev X, W
Section 2.1:
STM8A core
Section 2.1.1: Activation level (AL) bit not functional in Halt mode N
Section 2.1.2: JRIL and JRIH instructions not available N
Section 2.1.3: Main CPU execution is not resumed after an ISR
resets the AL bit
A
Section 2.1.4: Unexpected DIV/DIVW instruction result in ISR A
Section 2.1.5: Wait for event instruction (WFE) not available N
Section 2.1.6: Interrupt service routine (ISR) executed with priority of
main process
A
Section 2.2:
System
limitations
Section 2.2.1: HSI RC oscillator cannot be switched off in run mode N
Section 2.2.2: LSI oscillator remains on in Active-halt mode when
the AWU unit uses the HSE as input clock
N
Section 2.2.3: RAM content at address 0x000 not preserved after
RESET
A
Section 2.2.4: RAM modified after reset by embedded bootloader -
Section 2.2.5: Flash / EEPROM memory is read incorrectly after
wakeup from power down mode
A
Section 2.2.6: VDD rise-time rate for 100mV < VDD < 1V N
Section 2.3:
Timer peripheral
limitations
Section 2.3.1: Corruption of read sequence for the 16-bit counter
registers
A
Section 2.4:
LINUART
peripheral
limitations
Section 2.4.1: PE flag cannot be cleared during the reception of the
first half of Stop bit
A
Section 2.4.2: PE testing issue in UART mode N
Section 2.4.3: LIN mode: LIN header error when automatic
resynchronization is enabled
-
Section 2.4.4: LIN mode: framing error with data byte 0x00 N
Section 2.4.5: LIN mode: framing error when receiving an identifier
(ID)
N
Section 2.4.6: LIN mode: parity error when receiving an identifier
(ID)
N
Section 2.4.7: LIN mode: OR flag not correctly set in LIN Master
mode
N

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