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STM32L071V8 数据手册 - ST Microelectronics（意法半导体）
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STM32L071V8数据手册
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Contents STM32L071x8/B/Z
2/20 DocID027209 Rev 3
Contents
1 ARM 32-bit Cortex-M0+ limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 STM32L071x8/B/Z silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1.1 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . . 7
2.1.2 BFB2 bit does not select boot from Bank 2 system memory . . . . . . . . . . 8
2.1.3 Interrupts masked when using dual-bank boot mechanism . . . . . . . . . . 10
2.1.4 PE2 AF2 alternate function (TIM3_ETR) not available . . . . . . . . . . . . . 10
2.1.5 PB4 not available on UFQFPN32 package . . . . . . . . . . . . . . . . . . . . . . 10
2.1.6 Flash memory wakeup issue when waking up from Stop or Sleep
with Flash in power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.7 Unexpected system reset when waking up from Stop mode with
regulator in low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1.8 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1.9 I2C and USART cannot wake up the device from Stop mode . . . . . . . . 12
2.1.10 LDM, STM, PUSH and POP not allowed in IOPORT bus . . . . . . . . . . . 12
2.1.11 BOOT_MODE bits do not reflect the selected boot mode . . . . . . . . . . . 13
2.2 Comparator limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1 COMP1_CSR and COMP2_CSR lock bit reset by SYSCFGRST bit
in RCC_APB2RSTR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.2 Output of comparator 2 cannot be internally connected to input 1
of low-power timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3 RTC limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.3.1 Spurious tamper detection when disabling the tamper channel . . . . . . . 13
2.3.2 Detection of a tamper event occurring before enabling the tamper
detection is not supported in edge detection mode . . . . . . . . . . . . . . . . 14
2.4 I
2
C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.1 Wrong behaviors in Stop mode when waking up from Stop mode is
disabled in I
2
C peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.2 Wrong data sampling when data set-up time (t
SU;DAT
) is smaller than
one I2CCLK period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 SPI/I2S peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.1 In I2S slave mode, WS level must to be set by the external master
when enabling the I2S peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.2 BSY bit may stay high at the end of a SPI data transfer in slave mode . 16
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