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Transceiver Architecture in Cyclone V Devices
1
2016.01.28
CV-53001
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Describes the Cyclone
®
V transceiver architecture, clocking, channels, channel bonding, and transmitter
and receiver channel datapaths.
Altera
®
28-nm Cyclone V devices provide transceivers with the lowest power requirement at 3.125 and
6.144 Gigabits per second (Gbps). ese transceivers comply with a wide range of protocols and data rate
standards; however, 6.144 Gbps support is limited to the common public radio interface (CPRI) protocol
only.
Cyclone V devices have up to 12 transceiver channels with serial data rates between 614 megabits per
second (Mbps) and 6.144 Gbps and have backplane-capable transceiver support for PCI Express
®
(PCIe
®
)
Base Specication 2.0 Gen1 and Gen2 up to x4 bonded channels.
Cyclone V transceiver channels are full-duplex and clock data recovery (CDR)–based with physical coding
sublayer (PCS) and physical medium attachment (PMA) layers.
Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of
Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current
specications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice.
Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specications before relying on any published information
and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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