Datasheet 搜索 > FPGA芯片 > Altera（阿尔特拉） > 5CSEBA5U23C7S-N 数据手册 > 5CSEBA5U23C7S-N 其他数据使用手册 2/37 页
￥ 1140.639
5CSEBA5U23C7S-N 其他数据使用手册 - Altera（阿尔特拉）
制造商:
Altera（阿尔特拉）
分类:
FPGA芯片
封装:
UFBGA
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P31Hot
典型应用电路图在P5P7P9P11P13P15
型号编码规则在P5P7P9P11P13P15
封装信息在P2
导航目录
5CSEBA5U23C7S-N数据手册
Page:
of 37 Go
若手册格式错乱，请下载阅览PDF原文件
Advantage Supporting Feature
Lowest system cost
• Requires only two core voltages to operate
• Available in low-cost wirebond packaging
• Includes innovative features such as Configuration via Protocol
(CvP) and partial reconfiguration
Summary of Cyclone V Features
Table 2: Summary of Features for Cyclone V Devices
Feature Description
Technology • TSMC's 28-nm low-power (28LP) process technology
• 1.1 V core voltage
Packaging • Wirebond low-halogen packages
• Multiple device densities with compatible package footprints for seamless
migration between different device densities
• RoHS-compliant and leaded
(1)
options
High-performance FPGA
fabric
Enhanced 8-input ALM with four registers
Internal memory blocks • M10K—10-kilobits (Kb) memory blocks with soft error correction code
(ECC)
• Memory logic array block (MLAB)—640-bit distributed LUTRAM where
you can use up to 25% of the ALMs as MLAB memory
Embedded Hard IP blocks
Variable-precision
DSP
• Native support for up to three signal processing
precision levels (three 9 x 9, two 18 x 18, or one
27 x 27 multiplier) in the same variable-precision DSP
block
• 64-bit accumulator and cascade
• Embedded internal coefficient memory
• Preadder/subtractor for improved efficiency
Memory controller DDR3, DDR2, and LPDDR2 with 16 and 32 bit ECC
support
Embedded
transceiver I/O
PCI Express
®
(PCIe
®
) Gen2 and Gen1 (x1, x2, or x4)
hard IP with multifunction support, endpoint, and root
port
(1)
Contact Altera for availability.
2
Summary of Cyclone V Features
CV-51001
2014.10.06
Altera Corporation
Cyclone V Device Overview
Send Feedback
器件 Datasheet 文档搜索
AiEMA 数据库涵盖高达 72,405,303 个元件的数据手册，每天更新 5,000 多个 PDF 文件
