Datasheet 搜索 > 微控制器 > ATMEL（爱特美尔） > AT91SAM9G25-BFU 数据手册 > AT91SAM9G25-BFU 产品封装文件 2/1168 页
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AT91SAM9G25-BFU 产品封装文件 - ATMEL（爱特美尔）
制造商:
ATMEL（爱特美尔）
分类:
微控制器
封装:
VFBGA-247
Pictures:
3D模型
符号图
焊盘图
引脚图
产品图
页面导航:
引脚图在P11P13P14P15P16P17P18P19P20P21P22P23Hot
典型应用电路图在P53P541P614P742P758P839P963P1154
原理图在P4P31P37P52P79P113P127P145P153P161P170P175
封装尺寸在P1136P1137P1138P1139P1140P1141P1150P1157
型号编码规则在P1143P1150
标记信息在P1142
封装信息在P1137P1139P1141
功能描述在P56P81P114P128P146P154P162P222P334P350P377P441
应用领域在P79P949P1167
电气规格在P114P903P1105P1110P1149P1157
导航目录
AT91SAM9G25-BFU数据手册
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SAM9G25 [DATASHEET]
Atmel-11032F-ATARM-SAMG25-Datasheet_10-Mar-15
2
1. Features
Core
ARM926EJ-S™ ARM
®
Thumb
®
Processor running at up to 400 MHz @ 1.0V +/- 10%
16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
Memories
One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash, SDCard, DataFlash
®
or
serial DataFlash. Programmable order.
One 32-Kbyte internal SRAM, single-cycle access at system speed
High Bandwidth Multi-port DDR2 Controller
32-bit External Bus Interface supporting 4-bank and 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories
MLC/SLC 8-bit NAND Controller, with up to 24-bit Programmable Multibit Error Correcting Code (PMECC)
System running at up to 133 MHz
Power-on Reset Cells, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer
and Real Time Clock
Boot Mode Select Option, Remap Command
Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator
One PLL for the system and one PLL at 480 MHz optimized for USB High Speed
Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers
Dual Peripheral Bridge with dedicated programmable clock for best performance
Two dual port 8-channel DMA Controllers
Advanced Interrupt Controller and Debug Unit
Two Programmable External Clock Signals
Low Power Mode
Shut Down Controller with four 32-bit Battery Backup Registers
Clock Generator and Power Management Controller
Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
Peripherals
ITU-R BT. 601/656 Image Sensor Interface
USB Device High Speed, USB Host High Speed and USB Host Full Speed with dedicated On-Chip
Transceiver
One 10/100 Mbps Ethernet MAC Controller
Two High Speed Memory Card Hosts
Two Master/Slave Serial Peripheral Interface
Two 3-channel 32-bit Timer/Counters
One Synchronous Serial Controller
One 4-channel 16-bit PWM Controller
Three Two-wire Interfaces
Four USARTs, two UARTs, one DBGU
One 12-channel 10-bit Analog-to-Digital Converter
Soft Modem
Write Protected Registers
I/O
Four 32-bit Parallel Input/Output Controllers
105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input
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