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ATMEGA4809-AFR 产品修订记录 - Microchip（微芯）
制造商:
Microchip（微芯）
封装:
TQFP-48
描述:
ATMEGA4809-AFR 编带
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引脚图在P19P41P144P145P146P147P148P149P150P151P152P153Hot
原理图在P1P11P70P86P101P107P114P126P145P168P177P183
标记信息在P2
封装信息在P493
功能描述在P53P60P71P87P102P108P114P127P145P168P177P183
应用领域在P273P282P283P354
电气规格在P39P75P88P89P93P172P180P305P353P355P427
型号编号列表在P3
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ATMEGA4809-AFR数据手册
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Product Change Notification - SYST-27YEGS241
Date:
29 Mar 2019
Product Category:
8-bit Microcontrollers
Affected CPNs:
Notification subject:
Data Sheet - megaAVR 0-series Family Data Sheet
Notification text:
SYST-27YEGS241
Microchip has released a new DeviceDoc for the megaAVR 0-series Family Data Sheet of devices. If you are using one of these
devices please read the document located at megaAVR 0-series Family Data Sheet.
Notification Status: Final
Description of Change:
1) Entire document: Added support for ATmega808/809/1608/1609, Added support for 40-pin PDIP,
Editorial updates and Renamed document type from manual to family data sheet on the
2) Features: Updated data retention information and Extended speed grade information on the
Features section
3) Memories: Added oscillator calibration (OSCCALnnxn) registers; SIGROW- Updated description
to clarify that information is stored in fuse bytes, not in volatile registers; FUSE - Clarifying that
reserved bits within a fuse byte must be written to ‘0', Removed non-recommended BOD
levels in BODCFG, Updating access for LOCKBIT from R/W to R, Removed misleading reset values;
Updated Memory Section Access from CPU and UPDI on Locked Device section
4) AVR CPU: Removed redundant information
5) Clock Controller (CLKCTRL): Added OSC20MCALIBA register
6) Event System (EVSYS): STROBE/STROBEA renamed to STROBEx; Event Generators - Added
Window Compare Match for ADC, Updated TCB event generator description; Event Users- Updated
table; STROBEn - Updated access from R/W to W; Updated generator names in CHANNEL ;
Updated table in USER
7) PORTMUX - Port Multiplexer - Added explicit information for EVSYSROUTEA register
8) BOD - Brown-out Detector - Removed non-recommended BOD levels from CTRLB
9) TCA - 16-bit Timer/Counter Type A: Single Slope PWM Generation - Revised figure and
description; Dual Slope PWM - Revised figure and description; Events - Revised description and
added table
10) TCB - 16-bit Timer/Counter Type B : Updated block diagram for clock sources; Mode figures
legend use improved; Input Capture Pulse-Width Measurement mode figure corrected; 8-bit PWM
mode pseudo-code replaced by figure; Added output configuration table
11) Real-Time Counter (RTC): Clarified that first PIT interrupt and RTC count tick will be unknown;
Added Debug Operation section; Updated reset values for PER and CMP register; Updated access
for PITINTFLAGS register
12) USART - Universal Synchronous and Asynchronous Receiver and Transmitter: Structural
changes; General content improvements
13) Serial Peripheral Interface (SPI): Added INTCTRL register
14) Two-Wire Interface (TWI): Removed misleading internal information from Overview section;
Cleaned up Dual Control information; Clarified APIEN description in SCTRLA
15) CCL - Configurable Custom Logic: Register summary updated- Number n of LUTs and according
registers (LUTnCTRLA, LUTnCTRLB, LUTnCTRLC, TRUTHn); Update of terms and descriptions: -
Block Diagram section - CCL Input Selection MUX section - Sequencer Logic - Events - Filter -
Association LUT-Sequencer
16) Analog-to-Digital Converter (ADC): Updated ADC Timing Diagrams - Single Conversion - Free-
Running Conversion; Added information in the Events section
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