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EP2C20F484C6 产品修订记录 - Altera（阿尔特拉）
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Altera（阿尔特拉）
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FPGA芯片
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FBGA-484
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ALTERA Corporation 04/12/2006 PCN0603
PROCESS CHANGE NOTIFICATION PCN0603
Cyclone II Family M4K Memory Block Modification
Change Description:
The M4K memory block used in the Cyclone™ II device family is being modified to prevent
write errors that may occur under a rare set of conditions when configured in dual-port, dual-
clock mode. This modification may impact f
MAX
for certain M4K designs, as determined in
Quartus® II software version 5.1 SP2 and later.
Important information regarding performance optimization and programmer object file (.pof)
compatibility in specific versions of the Quartus II software is contained in the Cyclone II
FPGA Family Errata Sheet, located on the Altera® web site.
In accordance with JESD46-B, lack of acknowledgement of this notification within 30 days
constitutes acceptance of the change.
Reason for Change:
This change is to prevent errors that may occur under a rare set of circumstances when the
Cyclone II device M4K memory block is configured in the dual-port, dual-clock mode.
Products Affected:
This change affects all members of the Cyclone II product family. See Table 1 for a complete
list of the affected ordering codes.
Product Traceability and Transition Dates:
Production Cyclone II devices with the M4K memory block modification will start shipping
in the second quarter of 2006. The modified devices can be identified by the revision number,
as indicated in Figure 1.
Contact:
For more information on this change, contact your local Altera sales representative or Altera
Customer Quality Engineering at customer-quality@altera.com
.
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