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EP3C40F324I7N 产品描述及参数 - Altera（阿尔特拉）
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Altera（阿尔特拉）
分类:
FPGA芯片
封装:
FBGA-324
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EP3C40F324I7N数据手册
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1–6 Chapter 1: Cyclone III Device Family Overview
Cyclone III Device Family Architecture
Cyclone III Device Handbook July 2012 Altera Corporation
Volume 1
Table 1–5 lists Cyclone III device family configuration schemes.
Cyclone III Device Family Architecture
Cyclone III device family includes a customer-defined feature set that is optimized for
portable applications and offers a wide range of density, memory, embedded
multiplier, and I/O options. Cyclone III device family supports numerous external
memory interfaces and I/O protocols that are common in high-volume applications.
The Quartus II software features and parameterizable IP cores make it easier for you
to use the Cyclone III device family interfaces and protocols.
The following sections provide an overview of the Cyclone III device family features.
Logic Elements and Logic Array Blocks
The logic array block (LAB) consists of 16 logic elements and a LAB-wide control
block. An LE is the smallest unit of logic in the Cyclone III device family architecture.
Each LE has four inputs, a four-input look-up table (LUT), a register, and output logic.
The four-input LUT is a function generator that can implement any function with four
variables.
f For more information about LEs and LABs, refer to the Logic Elements and Logic Array
Blocks in the Cyclone III Device Family chapter.
Cyclone III
LS
EP3CLS70 — — — — — — C7, C8, I7 C7, C8, I7
C7, C8,
I7
EP3CLS100 — — — — — — C7, C8, I7 C7, C8, I7
C7, C8,
I7
EP3CLS150 — — — — — — C7, C8, I7 —
C7, C8,
I7
EP3CLS200 — — — — — — C7, C8, I7 —
C7, C8,
I7
Table 1–4. Cyclone III Device Family Speed Grades (Part 2 of 2)
Family Device E144 M164 P240 F256 U256 F324 F484 U484 F780
Table 1–5. Cyclone III Device Family Configuration Schemes
Configuration Scheme Cyclone III Cyclone III LS
Active serial (AS) v v
Active parallel (AP) v —
Passive serial (PS) v v
Fast passive parallel (FPP) v v
Joint Test Action Group (JTAG) v v
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