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H11G1SM 其他数据使用手册 - Fairchild（飞兆/仙童）
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Fairchild（飞兆/仙童）
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光耦合器/光隔离器
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Fairchild Semiconductor### 光耦合器，Fairchild Semiconductor
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H11G1SM数据手册
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SM320C6201B, SMJ320C6201B
DIGITAL SIGNAL PROCESSOR
SGUS031B -- APRIL 2000 -- REVISED AUGUST 2001
2
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
Table of Contents
parameter measurement information 30...............
signal transition l evels 30............................
input and output clocks 31...........................
asynchronous memory timing 34.....................
synchronous-burst memory timing 36.................
synchronous DRAM timing 40.......................
HOLD
/HOLDA timing 44............................
reset timing 45.....................................
external interrupt timing 47..........................
host-port interface timing 48.........................
multichannel buffered serial port timing 51.............
DMAC, timer, power -down timing 59..................
JTAG test-port timing 60............................
mechanical data 61.................................
description 2.........................................
device characteristics 3................................
functional block diagram 3..............................
CPU description 4.....................................
signal groups description 7.............................
signal descriptions 9...................................
development support 22...............................
device and development support nomenclature 23.........
documentation support 24..............................
clock PLL 26.........................................
power-supply sequencing 27...........................
absolute maximum ratings over operating case
temperature ranges 28............................
recommended operating c onditions 28...................
electrical characteristics over recommended ranges of
supply voltage and operating case temperature 29....
description
The 320C6201B DSP is a member of the fixed-point DSP family in the 320C6000 platform. The
SM/SMJ320C6201B (C6201B) device is based on the high-performance, advanced VelociTI
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an
excellent choice for multichannel and multifunction applications. With performance of up to 1600 million
instructions per second (MIPS) at a clock rate of 200 MHz, the C6201B offers cost-effective solutions to
high-performance DSP programming challenges. The C6201B is a newer revision of the C6201. The C6201B
DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array
processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent
functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of
parallelism and two 16-bit multipliers for a 32-bit result. The C6201B can produce two multiply-accumulates
(MACs) per cycle—for a total of 400 million MACs per second (MMACS). The C 6201B DSP also has
application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The C6201B includes a large bank of on-chip memory and has a powerful and diverse set of peripherals.
Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program
space. Data memory of the C6201B consists of two 32K-byte blocks of RAM for improved concurrency. The
peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a
host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM
or SBSRAM and asynchronous peripherals.
The C6201B has a c omplete set of development tools which includes: a new C compiler, a third-party Ada 95
compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface
for visibility into source code execution.
TI is a trademark of Texas Instruments Incorporated.
Windows is a registered trademark of the Microsoft Corporation.
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